- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... more
- RTX Corporation (Goleta, CA)
- …activities with cross-functional teams including chip architecture, specification, design , verification, validation, fabrication, packaging, debugging, test ... more
- Komatsu (Warrendale, PA)
- Electronics Hardware Design Engineer Date: Feb 26, 2025 Location: Warrendale, PA, US, 15086 Req ID: 30410 Onsite or Remote: Onsite Position Komatsu is an ... more
- The Boeing Company (El Segundo, CA)
- …Space & Security has an exciting opportunity as a **Lead Advanced Microelectronics Packaging Design Engineer ** . Come join us as part of our Electronics ... more
- Google (Sunnyvale, CA)
- …unparalleled performance, efficiency, and integration. As a Tensor Processing Unit (TPU) RTL Design Engineer , you will be part of a team developing ... more
- SpaceX (Irvine, CA)
- …environmental conditions specific to space applications + Work closely with the ASIC design team to add/improve testability and define various loopback ... more
- BAE Systems (San Diego, CA)
- …(Secret), or eligible to obtain one + Significant experience in FPGA (preferred) or ASIC Design / Development + VHDL (preferred) or Verilog HDL coding + ... more
- ManpowerGroup (Mountain View, CA)
- …who will thrive in this cutting-edge technical environment. **Job Title: Hardware Design Engineer 3** **Location: Mountain View, CA** **Job Responsibilities:** - ... more
- BAE Systems (Manchester, NH)
- …random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) + ... more
- BAE Systems (Manchester, NH)
- …random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) + ... more
- Qualcomm (Folsom, CA)
- …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design ... more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** Broadcom is lookign for ASIC implementation engineer with demonstrated expertise in multiple disciplines ... more
- Tarana Wireless (Milpitas, CA)
- …and system level integration, validation and troubleshooting + Perform FPGA level logic design , simulation, test , and debugging tasks + Participating in module ... more
- Google (Mountain View, CA)
- …design concepts, and languages such as Verilog or SystemVerilog. + Experience with ASIC design methodologies for clock domain checks, reset checks and low ... more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** Broadcom ASIC product division is a leader in semiconductor innovation, delivering ... more
- Qualcomm (San Diego, CA)
- …years. + Experience with Verilog/SystemVerilog design , Synopsys synthesis, low power design , test plan development, coverage-based design verification + ... more
- Qualcomm (San Diego, CA)
- …transformation to help create a smarter, connected future for all. The Digital ASIC Design Team is currently seeking candidates who will be responsible ... more
- Google (Mountain View, CA)
- …IPs, or other multimedia IPs such as Display or Video Codecs. + Experience with ASIC design methodologies for clock domain checks and reset checks. Be part of ... more
- Arrow Electronics (Cedar Rapids, IA)
- … (eInfochips Inc.) **Job Description:** **What You'll Be Doing:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, ... more
- Google (Madison, WI)
- …Work with architecture and power teams to evaluate features and their impact. + Work with design validation (DV) teams to create test plans to verify, and debug ... more