- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- SpaceX (Irvine, CA)
- Sr. SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX… more
- Western Digital (Irvine, CA)
- …be sold in millions of units. **Qualifications** + Hands-on experience in Firmware and ASIC -design Subgroups + SoC architectural level understanding + Strong ... in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering… more
- The LEGO Group (Boston, MA)
- …with the full SoC value chain, especially IP block integration within ASIC or custom silicon design. + Own RFx process with suppliers, supplier negotiations and ... enhancing its play experience with the technology elements, Semiconductors and SoC 's, Ecosystems, software management, application development and System … more
- NVIDIA (Santa Clara, CA)
- …(Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design, synthesis, timing + Silicon bring-up + SOC level integration What we need to see: + BS / MS in ... chance to work on architecture, design and synthesis for System - level modules for complex GPU and Tegra...from the crowd: + Familiarity with ARM CPU and SoC system architecture, microprocessor, and microcontroller fundamentals… more
- Micron Technology, Inc. (San Jose, CA)
- …for our storage-based controllers. + **Collaborative Design:** Work closely with other ASIC architects, system architects, and FW architects to define and ... Understanding of CPU and memory architectures, data path pipelining, distributed system design, ASIC low-power implementations, and clock/reset methodologies.… more
- Qualcomm (San Jose, CA)
- …power products. * Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system - level requirements. * ... IC Packages. * Writes and reviews detailed technical documentation for complex EDA/IP/ ASIC projects. ** Level of Responsibility:** * Works independently with… more
- Meta (Austin, TX)
- … Power Engineers within our Infrastructure organization to work on power/performance optimizations from SOC Architecture to System level . We are looking for ... 14. Experience with architectural performance and power models at SoC and system level 15.... systems for various design scales (IP blocks, SOC , multi-chip system ) with an understanding of… more
- Meta (Columbus, OH)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification. 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....and/or C/C++ based verification. 10. 10+ years experience in IP/sub- system and/or SoC level verification… more
- Meta (Columbus, OH)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification. 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization.... development cycles. 10. 5+ years of experience in IP/sub- system and/or SoC level verification… more
- Western Digital (Irvine, CA)
- …results in a fast-moving, dynamic environment. + Hands-On experience in Firmware and/or ASIC -design Subgroups + SoC architectural level understanding + ... From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and...As a Design Software Engineer in the Enterprise SSD System Design and Architecture Group you will design and… more
- SpaceX (Irvine, CA)
- …to solve complex problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with multicore CPU ... curious engineer who will work alongside world-class cross-disciplinary teams ( systems , firmware, architecture, design, validation, product engineering, ASIC … more
- Qualcomm (Santa Clara, CA)
- …concepts and C or C++ programming skills. + 5+ years of experience with developing either SoC level or Sub- system level or Block- level testbench ... team is responsible for the complete verification lifecycle, from system - level concept to tape out and post-silicon...similar methodologies. + Experienced in developing IP or Subsystem level or SoC level test… more
- Google (Sunnyvale, CA)
- …. + Work independently and collaboratively to create and review ASIC / SoC subsystem design architecture and microarchitecture specifications. + Develop ... from concept to silicon. + Experience interacting with software, system hardware, and other cross-functional teams. + Experience defining...SystemVerilog RTL to implement logic for ASIC / SoC products according to established coding and… more
- Cisco (San Jose, CA)
- …Bachelor's or Master's degree in equivalent experience. * Prior experience with ASIC verification using UVM/ System Verilog. * Prior experience verifying complex ... to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry,...blocks, clusters and top level for SoC * Prior experience building… more
- Qualcomm (Santa Clara, CA)
- …Engineer The team is responsible for the complete verification lifecycle, from system - level concept to tape out and post-silicon support. The responsibility ... UVM, system verilog, assertion, C++, python **Technology:** DDR, CACHE, SOC **Minimum Qualifications:** * Bachelor's degree in Science, Engineering, or related… more
- Meta (Sunnyvale, CA)
- …netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....for RTL-Synthesis and PrimeTime-STA for the blocks and the top- level including SOC . Analyze the inter-block timing… more
- NVIDIA (Santa Clara, CA)
- …Team is committed to deliver high-quality clocking and reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design has ... doing: + Own validation of Clocking structures in Tegra SOC GPU ASIC products from start to...profiling tools, X prop, etc. + Exposure on block level and system - level verification. +… more
- Tarana Wireless (Milpitas, CA)
- …teams to test the design on various emulation platforms + Work with Software and Systems teams on system verification and system integration + Writing test ... This position will challenge you! The Senior ASIC Engineer will work on complex ASIC...of Processors, Bus, Memory, and Interface IPs + Chip level integration and verification + RTL design and integration… more
- Amazon (Cupertino, CA)
- …right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a ... help you develop into a better-rounded professional. Custom SoCs ( System on Chip) live at the heart of AWS...rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies… more