- Qualcomm (San Diego, CA)
- …and implement multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer, you will work with microarchitecture and RTL ... power implementation methods + Knowledge of CPU microarchitecture, logic design and circuits ** Physical Requirements** + Frequently transports between… more
- NVIDIA (Hillsboro, OR)
- …meet performance, timing and power targets. + Deliver a synthesis/ timing clean design while working with the physical design team ensuring a routable ... We are looking for a Senior CPU Design Engineer! NVIDIA is seeking...with architects, design engineers, verification engineers, and physical design engineers teams to accomplish your… more
- Qualcomm (Austin, TX)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer, you will work with ... + Experience with Synthesis, place and route and signoff timing /power analysis. + Knowledge of high performance and low... design , Circuits, CAD) to solve key physical design problems in CPU … more
- Qualcomm (Raleigh, NC)
- … (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... coverage collection, gate level simulation, waveform viewers + C, C++, Python **_Digital Design /DV_** + RTL development for modem physical and MAC layer… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Experience with simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power implications. **Preferred… more
- Qualcomm (Austin, TX)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... expertise to improve PPA (power, performance and area) on CPU designs by collaborating with logic designers, physical...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... caches , working closely with the physical design team on implementation, synthesis and timing ...CPU team, you'll be a liaison between Logic design and Physical design teams… more
- NVIDIA (Santa Clara, CA)
- …aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts ... should be able to engage with multiple teams and design the GPU or CPU clocks to...other team members, we deliver clock information to GPU, CPU and SOC verification team, timing and… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Microsoft Corporation (Raleigh, NC)
- …to develop test plans and ensure functional correctness. + Interface with performance modeling, physical design , design for test, and other teams to optimize ... the logic design flow including RTL coding, RTL simulation, synthesis, timing constraints, timing closure. **Other Requirements:** + Ability to meet… more
- Cadence Design Systems, Inc. (Austin, TX)
- …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP + Design IP...and/or RISCV CPU and System IP + Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe,… more
- Cisco (San Jose, CA)
- … design bugs and close code coverage * Work closely with physical design team to close design timing and place-and-route issues * Triage, debug, ... participate in reviews * Implement Verilog RTL to meet timing and performance requirements * Help define, evolve, and...protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU 's is desirable * Design experience in… more
- SpaceX (Irvine, CA)
- …integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all phases of ASIC and/or ... FPGA design flow (eg synthesis, timing closure, formality...+ ASIC/SoC system integration experience + Experience with multicore CPU subsystem design + Experience with standard… more
- NVIDIA (Westford, MA)
- …designers to deliver best in class IP + partnering with our Physical Design team on partitioning, floorplanning and timing closure + providing design ... logic or lower layers of the OSI stack in general + in-depth understanding of physical design + strong working knowledge of Verilog or System Verilog + strong… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Chip, CPU Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for ... work at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are...tools including Genus Synthesis, Innovus P&R and Tempus Static Timing Analysis flows is expected. The Intern needs to… more
- Qualcomm (San Diego, CA)
- …+ Constraining and Timing Analysis experience + Physical Aware Synthesis + Physical Aware DFT + Physical Design + Clock tree Planning + Spine ... solutions for connecting various best in class IPs like CPU , GPUs, NSPs, Modems and to the latest best...Chip) which is highly floorplan driven. Also, as a Physical Architect engineer you will design architectures… more
- Cisco (San Jose, CA)
- … design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * Triage, debug, ... participate in reviews * Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and...protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU 's is desirable. * Design experience with… more
- Qualcomm (San Diego, CA)
- …develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing /PDN teams. Qualcomm is using leading ... compute and turn-around time reduction. + Provide solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket queues.… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …experience working on IC physical designs tools.Hands on experience using the above physical design tools for design closure and knowledge of physical ... critical step for various optimization objectives of a chip design , including timing (how fast a chip...variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI. The work done… more