- SpaceX (Irvine, CA)
- …closure in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power ... and timing closure + Work closely with chip architecture, design verification, physical design , DFT,...reconvergence pessimism removal + Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC,… more
- Amazon (San Diego, CA)
- …good communication and analytical skills. - Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites. ... is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer- STA to continue to innovate on behalf of our customers. We are a part… more
- Qualcomm (San Diego, CA)
- …domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements ... for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity… more
- Cisco (San Jose, CA)
- …and correlation between PNR, Spice, and STA , along with advising the Physical Design team on best practices. * Additionally, you'll develop methodologies, ... guidelines, and checklists to streamline STA work, resolve design and flow issues,...refining design and timing constraints for seamless physical design closure. As part of this… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should ... close tool bug fixes. Work on various aspects of physical design including timing analysis, place and...OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer… more
- Amazon (Cupertino, CA)
- … physical design , and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level of expertise in ... integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us...PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition ID:**… more
- The Boeing Company (Tukwila, WA)
- …Boeing Research & Technology is currently seeking a **Digital Integrated Circuit Physical Design Engineer (Associate, Mid-Level or Senior)** with experience ... but performs design (architecture, RTL, synthesis, circuits, physical design , verification, packaging and test) in...setup and hold violations, and perform static timing analysis ( STA ) to achieve timing closure. + Stay updated with… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX...and fix signoff closure issues in static timing analysis ( STA ), noise, logic equivalency, physical verification, electromigration… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation + Good understanding… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. ... amplify human inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block… more
- Broadcom (Irvine, CA)
- …STA , RTL/gate level simulations & silicon debug + Scripting for various IC design tasks such as STA , equivalency checks, test bench, simulations, synthesis, ... **Job Description:** + This opening is for working on chips that enable Physical Layer Products for High Speed Optical Communication. + architect block level … more
- Broadcom (San Jose, CA)
- …before you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure - ... partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able drive tools and methodologies… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... which is the primary task. + Develop flows/recommendations on STA and PNR in deep submicron physical ...sophisticated strategies of signing off timing in design for world-class silicon performance. + Develop tools, and… more
- Qualcomm (San Diego, CA)
- …static timing analysis ( STA ) for complex digital designs. - Collaborate with design , verification and PD teams to ensure timing closure and design ... for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC)… more
- Microsoft Corporation (Raleigh, NC)
- …to develop test plans and ensure functional correctness. + Interface with performance modeling, physical design , design for test, and other teams to optimize ... represent a variety of disciplines including, but not limited to, design , verification, and performance modeling, and DevOps supporting the development of… more
- Renesas (San Jose, CA)
- …in ATPG generation and ATE support is a plus + Experience in DFT or physical design is a plus + Experience with Verilog and/or SystemVerilog for digital ... methodology is a must + Competence in developing design constraints for synthesis, STA and P&R hand-off + Experience with gate-level simulations, causes… more
- Micron Technology, Inc. (Dallas, TX)
- …to ensure proper manufacturability of products. + Lead and collaborate with physical design , layout, and verification teams to deliver high-quality, on-time ... to enrich life. As the Director of HBM SoC Design , you will lead a team of HBM SoC...development capabilities and familiarity with IP level verification, synthesis, STA , and logic equivalence. + Knowledge of DRAM operation,… more
- Cadence Design Systems, Inc. (Austin, TX)
- …and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, synthesize RTL ... looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero… more