- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Physical Design and Timing Engineer - Intern to join our dynamic and ... something great, join us today! What you'll be doing: + You will drive physical design , power, and timing of high-frequency and low-power designs. + Help in… more
- Qualcomm (San Diego, CA)
- …crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements ... and bottlenecks. + Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. + Review and… more
- SpaceX (Irvine, CA)
- …and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to achieve ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer ...crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure… more
- Qualcomm (San Diego, CA)
- …in 5nm, 4nm and beyond (process technologies). + You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and ... cross-functional groups to determine product execution path. As a Timing Engineer , you will play a vital...have good execution knowledge. + Your contribution should improve timing convergence process across the company, design … more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the ... inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off...most sophisticated strategies of signing off timing in design for world-class silicon performance.… more
- NVIDIA (Westford, MA)
- …impact in a technology-focused company. What you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team,… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... level and/or blocks, with experience across the complete ASIC/SOC design flow including routing, static timing closure,...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design … more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding... design and implementation. + Hands-on experience in physical synthesis, floor planning, P&R, and timing … more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- The Boeing Company (Huntington Beach, CA)
- …us. Boeing Research & Technology is currently seeking a **Digital Integrated Circuit Physical Design Engineer (Associate, Mid-Level or Senior)** with ... physical design tools, including floor planning, placement, routing, and timing closure. + Familiarity with physical verification tools such as Calibre… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level +...**Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Physical Design Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive physical design and timing from netlist to gds. + Partner with mixed… more
- Cisco (Maynard, MA)
- …developing and optimizing physical floorplan and their implementation. What You'll Do The Physical Design Engineer Co-op will perform one or more of the ... and area optimization of design * Static Timing analysis and signoff closure * Physical ...VLSI design , and more specifically in ASIC physical design and verification * Interest and… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure - Drive IO/Core block physical… more
- Amazon (Portland, OR)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. ... Work hard. Have fun. Make history. As a Senior Physical Design Engineer , you will:...pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... caches , working closely with the physical design team on implementation, synthesis and timing ...between Logic design and Physical design teams responsible for achieving timing , area,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...+ Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop… more
- Amazon (San Diego, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. ... design such as Clocking, Power Delivery and Partition synthesis/APR. - Drive physical design and timing closure including FEV, LVS, DRC, and reliability… more
- Capgemini (Auburn Hills, MI)
- …_Programmer/Analyst_ **Organization:** _ERD PPL US_ **Title:** _Mechanical & Physical Engineer - Automotive Electric Drive Module Design & Release Engineer_ ... We are seeking an Associate Design & Release Engineer to join...and risk management. + Lead efforts to achieve program timing turning points by successfully coordinating tasks, resources, and… more