• Sr. SOC/ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
    SpaceX (08/24/24)
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  • Senior Silicon Engineer PD CAD…

    Microsoft Corporation (Mountain View, CA)
    …of Artificial Intelligence and Computing. We are looking for a **Senior Silicon Engineer ** to join our team! If you are like tackling complex Register Transfer ... Logic ( RTL ) /Implementation challenges and have a keen interest in...checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites… more
    Microsoft Corporation (11/12/24)
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  • SoC UPF Design Engineer , Google Cloud

    Google (Sunnyvale, CA)
    …field, or equivalent practical experience. + 3 years of experience with RTL coding using Verilog/SystemVerilog. + 2 years of experience with industry-standard tools, ... role, you will join a team working on SoC-level RTL design for our data center accelerators. In this...transitions, and isolation strategies. + Take ownership of power signoff using industry standard tools coordinating deliverables from block… more
    Google (11/15/24)
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  • CPU Physical Design Engineer

    Qualcomm (San Diego, CA)
    …multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer , you will work with microarchitecture and RTL design team to ... smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU)...implementability, area, timing and power. + Synthesize the Verilog RTL into gate level designs and perform optimizations. +… more
    Qualcomm (10/25/24)
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  • Sr. SOC Design Engineer - STA, Hardware…

    Amazon (San Diego, CA)
    …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer -STA to continue to innovate on behalf of our customers. We are a part of ... history. Roles & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA, Crosstalk… more
    Amazon (11/16/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    …physical design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities ... primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip...silicon validation phases with additional exposure to physical design signoff activities. What You'll Do You will be part… more
    Cisco (10/23/24)
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  • Sr. SOC/ASIC Physical Design Engineer

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
    SpaceX (11/15/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    …Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ... and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do * Responsible for implementing the Hardware… more
    Cisco (11/01/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    …Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ... flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do * Responsible for thorough test planning and… more
    Cisco (10/17/24)
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  • Senior E/E & Semiconductor Engineer - ASIC…

    Capgemini (San Francisco, CA)
    **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, ... executing from the inception of the design ( RTL or gate netlist) through the tape-out release to...about 1 GHz *Experience with low power implementation and signoff , power gating, multiple voltage rails, UPF knowledge. *Experience… more
    Capgemini (10/16/24)
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  • Sr. Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... to improve turnaround times for physical design work. Interface directly with RTL , Physical Design, Package Design, DFT and other teams to improve methodologies… more
    Amazon (10/18/24)
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  • CPU Physical Design Methodology Engineer

    Qualcomm (Austin, TX)
    …Group > CPU Engineering **General Summary:** As a CPU Physical Design Methodology Engineer , you will work with implementation and CAD teams to implement the designs ... of practical experience + Experience with Synthesis, place and route and signoff timing/power analysis. + Knowledge of high performance and low power implementation… more
    Qualcomm (10/31/24)
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  • Physical Design Engineer

    Broadcom (Colorado Springs, CO)
    …looking for highly skilled engineers that want to be part of an RTL to GDS team, enabling high-speed chip implementations, reducing power, increasing performance and ... - Expertise in Physical Design, Synthesis, EM/IR, Physical Verification, Timing Signoff - Understanding of Clock structures, Power optimization, DFT - Deep… more
    Broadcom (11/01/24)
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  • Implementation Timing / STA Design Engineer

    Qualcomm (San Diego, CA)
    …synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL ... design and physical design teams to identify timing requirements and bottlenecks. + Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. + Review and integrate HM constraints into SoC and… more
    Qualcomm (09/04/24)
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