- Qualcomm (Santa Clara, CA)
- …based verification skills, experience with assertions, and coverage-based verification methodology + Strong leadership, Analytical and problem-solving skills ... complex IP blocks and subsystems. **Job Responsibilities** + Lead Sub-System & SoC Design verification for Qualcomm WIFI projects + Own end-end low power test… more
- Microsoft Corporation (Hillsboro, OR)
- …trusted experience to customers and partners worldwide and we are looking for a ** SoC Hardware (Digital, Analog or PnP) Validation Engineer ** to help achieve ... scale and sustainability related to Microsoft cloud hardware. We are looking for a ** SoC Hardware (Digital, Analog or PnP) Validation Engineer ** with a passion… more
- Microsoft Corporation (Hillsboro, OR)
- …to customers and partners worldwide and we are looking for a **Senior SoC Hardware (Analog/Power) Validation Engineer ** to help achieve that mission. Microsoft's ... day. **Responsibilities** The Silicon computing development team is seeking a **Senior SoC Hardware (Analog/Power) Validation Engineer ** to join the post-silicon… more
- SpaceX (Irvine, CA)
- Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...with power intent and upf development for block and soc top. + Familiar with formal verification … more
- Qualcomm (San Diego, CA)
- …to join a fast-paced SoC team responsible for RTL Design, flows and methodology for high performance ASICs in sub-5nm process nodes for mobile, AI, Compute and ... sound ASIC engineering practices with minimal supervision + Executes the design and verification strategies according to ASICs, SoC , and IP cores specifications… more
- Amazon (San Diego, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer -STA to continue to innovate on behalf of our customers. We ... STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners, Synthesis, Place & Route… more
- Meta (Redmond, WA)
- **Summary:** As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... cases for multiple state of the art SOCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects defining… more
- Meta (Columbus, OH)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Columbus, OH)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to...at NVIDIA. + Work closely with software, architecture, design, verification , and silicon validation teams. + Train and mentor… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model… more
- Qualcomm (Santa Clara, CA)
- …controller, Coherent Interconnects, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, ... field is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + Master's degree… more
- Capgemini (Santa Clara, CA)
- **Job Title:** **Design Verification Engineer ** **Job Location: Santa Clara CA** **Job description:** *Architect and Create verification environments using ... System-Verilog and Universal verification methodology -UVM IPs and SoCs with embedded CPUs and analog...in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex Microcontroller… more
- Meta (Austin, TX)
- …and UVM methodology . 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 10. Experience ... through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you...the testing infrastructure to validate new core IP or SoC implementations. You will work closely with researchers, architects… more
- Meta (Redmond, WA)
- … and methodology development. **Required Skills:** Analog & Mixed Signal Verification Engineer Responsibilities: 1. Lead AMS IP/chip verification , ... products. We are seeking an Analog and Mixed Signal Verification engineer to lead analog mixed signal...mixed signal SoC . 18. Experience in developing verification methodology , flows and automation. 19. Experience… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...plans based on the Architecture and Micro-architecture. + Develop Verification Methodology , ensuring scalability and portability across… more
- Northrop Grumman (San Diego, CA)
- …history, they're making history. Explore a career engineering what's possible as a Digital Verification Engineer in San Diego, CA. **What You'll Get to Do:** Our ... the beach Southern California is famous. As a Digital Verification Engineer at Northrop Grumman, you will...design (Memories, bus standards, microprocessors) + Experience with functional verification methodology for the full life cycle… more
- Northrop Grumman (San Diego, CA)
- …history, they're making history. Explore a career engineering what's possible as a Digital Verification Engineer in San Diego, CA. **What You'll Get to Do:** Our ... beach Southern California is famous for. As a Digital Verification Engineer at Northrop Grumman, you will...design (Memories, bus standards, microprocessors) + Experience with functional verification methodology for the full life cycle… more
- NVIDIA (Austin, TX)
- The NVIDIA System-On-Chip ( SOC ) group is looking for a top ASIC Verification Engineer interested in innovative approaches to drive design quality in our IP. ... efficiently build, deploy, and verify generated RTL + Build verification components using SV/UVM methodology + Driving coverage based verification closure +… more
- Capgemini (San Francisco, CA)
- …UVM (Universal verification ) methodology for IP verification . IP verification must have and SoC verification good to have. **Key ... **Job role:** **Lead DV IP Verification Engineer ** **Job Location : San Francisco CA / Sunnyvale CA** **Job description:** Architect and Create verification … more