• Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are seeking an innovative Custom Circuits Timing Methodology Engineer to help drive sign-off strategies for the ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
    NVIDIA (09/12/24)
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  • Senior Timing Methodology

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for ... Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones...transistor level along with ones using standard cells and custom designs. + Validating the timing of… more
    NVIDIA (07/27/24)
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  • Semi- Custom Design Methodology

    NVIDIA (Santa Clara, CA)
    NVIDIA is hiring a SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals ... What you will be doing: + Responsible for developing and optimizing semi- custom design methodologies, work with internal and external collaborators and IP Vendors… more
    NVIDIA (07/23/24)
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  • SRAM Timing Engineer

    NVIDIA (Santa Clara, CA)
    …power NVIDIA's next generation of AI chips. What you will be doing: + Drive robust methodology for timing analysis of custom circuit IP. + Support SRAM and ... the world! We are currently looking for a SRAM Timing Engineer to join our team of...other custom circuit design engineers through successful timing convergence towards tape-out. + Work closely with design… more
    NVIDIA (07/23/24)
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  • Senior Principal Electrical Engineer

    Renesas (Austin, TX)
    Senior Principal Electrical Engineer Job Description The Performance Computing Power (PCP) group is seeking an experienced Digital IC Designer to join our expanding ... business focused on power management and multiphase solutions for CPUs and custom ASIC power. **Responsibilities:** + **Product Definition:** Play a critical role in… more
    Renesas (08/14/24)
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  • CPU Physical Design Sr. Staff CAD Engineer

    Qualcomm (Santa Clara, CA)
    …envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the world's best implementation tools and ... flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. **Minimum Qualifications:** * Bachelor's degree in… more
    Qualcomm (07/23/24)
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  • CAD Engineer - TPG

    Micron Technology, Inc. (Atlanta, GA)
    …tools and flows for the design, implementation, verification, & tape out of custom memory designs! These CAD tools & collateral enable DRAM, NAND, and other ... software and system development within the highly specialized domain of custom IC design and implementation. **Responsibilities** **:** + Perform day-to-day support… more
    Micron Technology, Inc. (06/21/24)
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  • Sr. Silicon ATE Engineer , Project Kuiper

    Amazon (Sunnyvale, CA)
    …an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of ... the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design… more
    Amazon (08/16/24)
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  • SPF/Spice CAD Engineer - TPG

    Micron Technology, Inc. (Dallas, TX)
    …tools and flows for the design, implementation, verification, & tape out of custom memory designs! These CAD tools and collateral enable DRAM, NAND, and other ... teams. The tools and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design, custom layout, parameterized cells,… more
    Micron Technology, Inc. (07/26/24)
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  • Chip Package Signal and Power Integrity…

    Google (Sunnyvale, CA)
    …budget. + Familiarity with memory testing, next generation memory, chiplet standards and timing budget methodology . Be part of a diverse team that pushes ... boundaries, developing custom silicon solutions that power the future of Google's...integration. As a Chip Package Signal and Power Integrity Engineer you will be responsible for the chip package… more
    Google (09/07/24)
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  • Principal IO Design Engineer , HBM Design

    Micron Technology, Inc. (Folsom, CA)
    …information to enrich life. We are looking for a HBM High-speed IO Design Engineer . Are you passionate about crafting circuits for the next generation of memory that ... and AI (Artificial Intelligence). HBM incorporates RTL-style logic design, custom high-speed PHY design, analog circuit design, and DFT...DLL, CDR, high-speed data path. + Link budget and timing closure + Participate in new circuit conception and… more
    Micron Technology, Inc. (07/25/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation...be. What you'll be doing: + Work in NVIDIA's semi- custom engineering team building customized chip solutions targeting data… more
    NVIDIA (07/23/24)
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  • Physical Implementation Engineer

    Qualcomm (San Diego, CA)
    …technology + Circuit Design + STA timing + Power analysis + Semi- custom design flow and methodology **Principal Duties and Responsibilities:** * Works across ... direct reports (only applies to positions with direct reports). + PNR/Synthesis tools, flows and methodologies + SOC Design implementation / methodology + Process… more
    Qualcomm (08/06/24)
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  • Sr. Program Manager - CPU IP

    Qualcomm (Austin, TX)
    …will be responsible for providing technical program management support to our Custom CPU Engineering team including the following responsibilities: * Work with ... project execution from Synthesis through GDSII including domain signoffs ( Timing , PDN, PDV) * Lead the creation and maintenance...or PhD degree in Engineering * Experience as an engineer in chip development and integration into hardware or… more
    Qualcomm (07/12/24)
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