- Textron (Wilmington, MA)
- ** UVM Design Verification Engineer III** **Description** \!\ * \! **_Who We Are_** Textron Systems is part of Textron, a $14 billion, multi\-industry ... and ASIC designs for our electronic systems\. The FPGA/ASIC Design Verification Engineer will be...designs * Develop test benches for FPGA or ASIC design verification using UVM , System… more
- US Tech Solutions (Goleta, CA)
- **Job Description:** + As an FPGA design engineer , you will take ownership of project components and develop scalable RTL that meets timing requirements. + ... a key role in creating and executing test plans to validate your design features. + Additionally, you will be responsible for developing proof-of-concept designs… more
- The Boeing Company (Mesa, AZ)
- …We are seeking **Lead or Senior** **Field Programmable Gate Array (FPGA) Universal Verification Methodology ( UVM ) Advanced Verification Engineers** who are ... skills and capabilities in all areas of the FPGA verification lifecycle to include architecting UVM /UVMF test...breadth of the Boeing Avionics products. As an Advance Verification FPGA Engineer on the Boeing AvionX… more
- ManpowerGroup (Redmond, WA)
- …Client, a worldwide technology corporation, is seeking an experienced Hardware Design Verification Engineer with expertise in UVM for an 18-month ... contract assignment. As a Hardware Design Verification Engineer on this...be team-oriented and have deep experience with block level verification and UVM library and methodology to… more
- Meta (Columbus, OH)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...responsible for the verification closure of a design module or sub-system from test-planning, UVM … more
- Meta (Columbus, OH)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...responsible for the verification closure of a design module or sub-system from test-planning, UVM … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...responsible for the verification closure of a design module or sub-system from test-planning, UVM … more
- SpaceX (Irvine, CA)
- Wireless Modem Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is ... goal of enabling human life on Mars. WIRELESS MODEM DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)...in electrical engineering or computer engineering + Experience with verification methodologies such as UVM + Strong… more
- Meta (Austin, TX)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1....13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
- Meta (Redmond, WA)
- **Summary:** As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your ... and test cases for multiple state of the art SOCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and… more
- Meta (Sunnyvale, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1....14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more
- Capgemini (Santa Clara, CA)
- **Job Title:** ** Design Verification Engineer ** **Job Location: Santa Clara CA** **Job description:** *Architect and Create verification environments ... using System-Verilog and Universal verification methodology- UVM IPs and SoCs with embedded CPUs and analog...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_… more
- Capgemini (San Francisco, CA)
- **Job Title: Design Verification Infrastructure Engineer ** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job Description:** **Key Responsibilities:** ... + .Assist the design verification leads to develop software for...environments (Bash scripting, Makefile) + .Experience in development of UVM based verification environments is plus +… more
- Amazon (Boise, ID)
- …Fire tablets, Fire TV and Amazon Echo. What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will be part of an advanced ... across multiple disciplines - Deliver detailed test plans for verification of complex digital design blocks by... engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and… more
- Qualcomm (Santa Clara, CA)
- …This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog- UVM , coverage development, assertion model… more
- NVIDIA (Santa Clara, CA)
- We're now looking for a Senior Digital Design Verification Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... join our diverse team today! As a Senior Digital Design Verification Engineer at NVIDIA,...models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM . + Build… more
- Capgemini (Sunnyvale, CA)
- …**Sunnyvale CA - Onsite role** **Job description:** We are seeking Mixed signal Design Verification Engineer who is proficient in system verilog ... Familiarity with writing regression tests for analog behavioral model verification + Hands on experience with UVM ...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification Engineer_… more
- Qualcomm (Santa Clara, CA)
- …controller, Coherent Interconnects, its testbench development using the advanced verification methodology such as SystemVerilog- UVM , coverage development, ... is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and methodology...environment using SystemVerilog + 5+ years of experience with verification methodologies such as UVM or OVM… more
- Qualcomm (San Diego, CA)
- …for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog- UVM , coverage development, assertion model ... or a closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and methodology **Preferred Qualifications** + Master's… more
- NVIDIA (Belfast, ME)
- …Data Processing Units (DPUs), which are revolutionising today's Data Centre. As a Senior Chip- Design Verification Engineer , you will join a group of ... NVIDIA is looking for a Senior Verification Engineer to join our Networking Chip Design ...and BlueField SoC (System-on-Chip) silicon teams + Use advanced verification methodologies like e/Specman and SystemVerilog/ UVM to… more