• ASIC Formal Verification

    Amazon (Austin, TX)
    …be responsible for defining and checking the specification of critical hardware modules using formal methods and industrial model checkers. You will be a part of a ... 2025 and September 2026 - Completed coursework or prior internship experience with formal methods (SW/HW) - Coursework or prior internship experience in the basics… more
    Amazon (10/04/24)
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  • ASIC Engineer , Design…

    Meta (Columbus, OH)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
    Meta (11/09/24)
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  • ASIC Engineer , Design…

    Meta (Columbus, OH)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation. 20.… more
    Meta (11/05/24)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …You Are The Core Hardware Business Unit is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation of Silicon One ... of related ASIC design verification experience. * Proficient in ASIC verification using UVM/System Verilog. * Proficient in verifying complex blocks,… more
    Cisco (10/01/24)
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  • ASIC Engineer , Design…

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The...teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:… more
    Meta (11/20/24)
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  • Sr. ASIC Design Verification

    Qualcomm (Santa Clara, CA)
    …such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Involve in developing automation ... field is preferred + 5+ years of experience with ASIC design and verification tools, techniques, and...not mandatory + Knowledge or experience with Assertion Based Formal Verification is desirable but not mandatory… more
    Qualcomm (10/14/24)
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  • ASIC Design Verification

    Qualcomm (San Diego, CA)
    …such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware ... closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and...as UVM or OVM and exposure to Assertion based Formal Verification + 3+ years of experience… more
    Qualcomm (09/18/24)
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  • ASIC Design Verification

    Qualcomm (Santa Clara, CA)
    …products. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete ... such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware… more
    Qualcomm (11/21/24)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …and Python/Perl are preferred. * Knowledge of Networking is preferred. * Experience with Formal verification is a plus. Why Cisco? #WeAreCisco. We are all ... shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation models,… more
    Cisco (10/28/24)
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  • Senior ASIC Verification

    NVIDIA (Santa Clara, CA)
    The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage… more
    NVIDIA (10/16/24)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …You'll Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely ... engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC...MMU. * Experience with Veloce/HAPS is a plus * Formal verification (iev/vc formal ) knowledge… more
    Cisco (11/01/24)
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  • ASIC Design Verification Staff…

    Qualcomm (Santa Clara, CA)
    … methodology + Strong debugging, Analytical and problem-solving skills + Experience in formal / static verification methodologies will be a plus + Good ... Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification , validation, integration, or related work experience. OR… more
    Qualcomm (09/23/24)
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  • ASIC Verification Engineer

    Cisco (San Jose, CA)
    …experience with System Verilog / UVM programming * 4+ Years post graduate ASIC Verification processes, methodologies, flows and tools * Experience with scripting ... work with SDK and Software teams as part of ASIC development to create a flawless handshake between hardware...Understanding of Networking technologies and concepts * Experience with Formal verification * Experience with Post-silicon lab… more
    Cisco (11/24/24)
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  • Sr. ASIC Design Verification

    Amazon (Austin, TX)
    …in the validation of FPGAs using test benches, which can be reused for the ASIC implementation . Run formal verification of complex blocks to ensure ... in communication systems - Familiarity with Matlab - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is committed… more
    Amazon (11/16/24)
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  • ASIC Verification Engineer

    Amazon (Redmond, WA)
    …Master's or Ph.D degree in Electrical / Communications Engineering. - Familiarity with formal verification techniques. - Familiarity with Matlab. - Experience in ... sub-team responsible for defining and implementing Application Specific Integrated Circuit ( ASIC ) devices used for communication links between low Earth orbit (LEO)… more
    Amazon (11/26/24)
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  • Sr. SOC/ ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …chip and block level front-end implementation from timing constraints development, synthesis, formal verification , power intent generation & validation + Develop ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...various IPs into RTL + Develop/modify/run RTL logic synthesis, formal verification , power intent verification more
    SpaceX (11/22/24)
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  • ASIC Verification Engineer

    Amazon (Sunnyvale, CA)
    …digital verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - ... highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team… more
    Amazon (11/20/24)
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  • Low Power ASIC Engineer (Next-Gen,…

    Qualcomm (San Diego, CA)
    …power, high performance ASIC /SoC design flows (micro-architecture, RTL design, verification , synthesis, timing/STA, UPF, CLP, LEC formal verification , ... compute, AI and XR space. An ideal candidate will oversee definition, design, verification , and documentation for ASIC development for a variety of products.… more
    Qualcomm (11/16/24)
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  • ASIC Engineer

    Cisco (San Jose, CA)
    …What You'll Do The Core Hardware Business Unit is looking for a motivated Senior Verification engineer /lead to engage in new development of our UCS family. You ... Master's degree in equivalent experience. * Prior experience with ASIC verification using UVM/System Verilog. * Prior...* Prior experience with Veloce/Palladium/Zebu/HAPS * Prior experience with formal verification (iev/vc formal ) We… more
    Cisco (10/01/24)
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  • ASIC Engineer Intern, Design

    Meta (Austin, TX)
    … engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Design Responsibilities: 1. Participate in Micro-architecture, ... **Summary:** Meta is seeking an ASIC Design Engineer Intern to join...will have an opportunity to participate in design and verification of advanced IPs using state of the art… more
    Meta (11/02/24)
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