- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities: 1. Develop and own physical … more
- Amazon (Cupertino, CA)
- …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity… more
- Cisco (San Jose, CA)
- …now has a new faster, better, safer engine! Your Impact You'll be joining our Physical Design team at Cisco Silicon One group, which is responsible for the ... Electrical Engineering or equivalent similar experience * 10+ years experience in physical design with a minimum 4 years working on Fullchip activities *… more
- Broadcom (San Jose, CA)
- …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
- SpaceX (Irvine, CA)
- …clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on physical design and timing closure + Familiar with ASIC synthesis and ... timing/power optimization engineering change order flows (Timing ECOs) and integrate them into physical design flow + Work with systems and architecture, SOC… more
- NVIDIA (Santa Clara, CA)
- …interconnect and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early ... We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is...What you will be doing: + Working with architects, design leads, physical design leads… more
- Cisco (San Jose, CA)
- …and implementation of SDC for various timing modes in the chip. * Collaborating with physical and ASIC design teams to resolve timing and routing congestion ... will act as a bridge between cross-functional teams, including physical design , verification, and software, to ensure...Electrical or Computer Engineering with 10 Years Experience with ASIC design timing closure flow (STA) and… more
- Cisco (San Jose, CA)
- …to physical design signoff activities. What You'll Do You will be part of ASIC physical design Team which is responsible for full Chip physical ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture...Science, with 7+ year minimum of hands-on experience in ASIC implementation and Physical verification * Prior… more
- Amazon (Cupertino, CA)
- …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... - BS + 4yrs or MS + 3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block … more
- Google (Mountain View, CA)
- …chip design tools. Minimum Qualifications: + At least 10 years experience in ASIC physical design flows and methodologies in advanced nodes. + Experience ... in a research environment. + Hands on experience and a solid understanding of ASIC physical design , physical design flows and methodologies including… more
- Amazon (Cupertino, CA)
- …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place and route,… more
- Broadcom (Fort Collins, CO)
- …+ Professional, open, and highly self-motivated attitude + Strong understanding of VLSI and ASIC physical design + Should have basic understanding of PLLs ... team of engineers that own and provide the flows that enable our ASIC design teams. This position would focus on developing, testing, and enhancing our STA… more
- Broadcom (San Jose, CA)
- …high overall manufacturing yield. The candidate should have a strong understanding of VLSI and ASIC physical design 12+ years of experience w/ a deep ... that will lend itself to seamless closure in the physical design backend flows, help define and...understanding of ASIC architecture, design , development and verification. -… more
- Amazon (San Diego, CA)
- …Engineering. * 10+ years of experience in ASIC implementation. * Experience in leading physical design . * Strong exposure to UPF flow for low power design ... you will set up the flow for both logic and physical synthesis flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the… more
- NVIDIA (Santa Clara, CA)
- …opportunity to build sophisticated GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design , CAD, Package Design , Software, DFT ... NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design...design quality checks and reviews to present the physical design team with high-quality RTL What… more
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