- Cisco (San Jose, CA)
- …execution to ensure progress and accuracy. Who you are You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing ... most complex ASICs being developed. Who you'll work with You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in… more
- Amazon (San Diego, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer - STA to continue to innovate on behalf of our customers. We are a part ... development of signoff methodology and corresponding implementation solution - Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs.… more
- SpaceX (Irvine, CA)
- …or computer science + 5+ years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer /Senior: $170,000.00 - $230,000.00/per year Your… more
- Qualcomm (San Diego, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run Logic/Physical Synthesis using ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....for RDC. 8. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- Qualcomm (San Diego, CA)
- … ASIC /SoC design flows (micro-architecture, RTL design, verification, synthesis, timing/ STA , UPF, CLP, LEC formal verification, DFT, physical design.) + Hands-on ... company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and...skills, and a focus on low power, high performance ASIC designs, and, ability to execute critical power analysis… more
- ManpowerGroup (Phoenix, AZ)
- **SOC Integration/ STA /Synthesis Engineer ** Required Skills: + Develop and own physical design implementation of multi-hierarchy low-power designs including ... ECO in advanced technology nodes + Develop & document STA & Synthesis strategies. Interact with methodology teams to...physical design of an end-to-end IP or integration of ASIC /SoC design Minimum Qualifications: + Bachelor's degree in Electrical… more
- Northrop Grumman (Baltimore, MD)
- …you to join our team as a Principal Digital Engineer /Senior Principal Digital Engineer (FPGA and ASIC Design) based out of Linthicum, MD. **What You'll get ... team in Mission Systems that encompasses Digital Engineering to support FPGA and ASIC product development. + Work closely with design engineers and will utilize your… more
- L3Harris (Camden, NJ)
- Job Title: Lead ASIC /FPGA VHDL Design Engineer Job Code: 15340 Job Location: Camden, NJ (relocation can be provided for those that qualify) Schedule: 9/80 ... with every other Friday off Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff (SMES) will be part of the… more
- Micron Technology, Inc. (Minneapolis, MN)
- …environment, and groundbreaking technology while rapidly growing your abilities. As our Staff ASIC Digital Synthesis Engineer role, you will contribute to the ... you will develop and operate front-end Synthesis flows, including STA , constraint management, Lint/CDC/RDC, front-end/back-end netlist handoff, formal checks, design… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Amazon (Hawthorne, CA)
- …front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining ... test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans - Write high quality documents to guide a scalable team Basic Qualifications - Bachelor's degree in Electrical Engineering, Communications Engineering or… more
- Google (Mountain View, CA)
- …in Physical Implementation of High Performance ASICs. + Experience building ASIC implementation flows (RTL-to-GDS2). Preferred qualifications: + Master's degree or ... field. + Experience as technology lead driving Physical Implementation for complex ASIC project(s). + Experience with pre-silicon and post-silicon Design For Test… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... You'll Be Doing: + Develop and validate flows for PT- STA regression, analysis, QOR metrics for high-speed designs. The...Electrical or Computer Engineering with 5 years' experience in ASIC Design and Timing. + Good knowledge of extraction,… more
- Qualcomm (Austin, TX)
- …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU...Layout Parasitic Extraction, feed through handling, + Knowledge of ASIC back-end design flows and methods and tools (ICC2,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes RTL integration, maintain the timing constraint, ... Synthesis, Place and Route, Static timing analysis ( STA ), timing closure, power optimization, and physical verification for both of block and Chip top level You will… more
- Honeywell (Moca, PR)
- As a Semiconductor Engineer I - (Electrical Circuit Design Engineer ) here at Honeywell Puerto Rico, you will be accountable for the design and development of ... detail will ensure the successful development and optimization of ASIC design projects. You will report directly to our...the design. * Development of the Static Timing Analysis ( STA ) constraints for physical construction and timing closure in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. The position is part of Palladium ASIC development team . The team is responsible for all the ASICs that go into the ... of the usage modes and debug tools. The Palladium ASIC team has a wide range of expertise from...Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint… more