- Qualcomm (Santa Clara, CA)
- …the definition and design of Platform infrastructure HW components such as Memory controllers, System cache , System MMU and Interconnect that are implemented ... both Infra IP level u-architecture optimizations as well as System level application performance verification . The ideal...architecture and design decisions. + Modeling and analysis of system cache , replacement algorithms, and features +… more
- Skyworks (Austin, TX)
- …synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. + Verification of digital sub - systems , mixed-signal sub - systems ... (eg Matlab, C), scripting languages (eg Tcl, Perl, Python, SKILL), and version control systems (eg SVN, SOS) Working knowledge of System Verilog and/or UVM… more
- Skyworks (Nashua, NH)
- …synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. + Verification of digital sub - systems , mixed-signal sub - systems ... (eg Matlab, C), scripting languages (eg Tcl, Perl, Python, SKILL), and version control systems (eg SVN, SOS) Working knowledge of System Verilog and/or UVM… more
- Qualcomm (Austin, TX)
- … (micro-architecture) + Demonstrated deep technical knowledge and achievements at the SoC, sub - system or large IP levels as micro-architect or architect + ... the better) + SoC architectures including heterogeneous compute, NoC/interconnect, memory- systems , multicore, multi-die, cache hierarchies, shared memory, I/O,… more
- Microsoft Corporation (Raleigh, NC)
- …will: + Be part of a design team developing advanced components of the memory sub - system . + Own multiple blocks within a complex, coherent fabric and bridge IP. ... represent a variety of disciplines including, but not limited to, design, verification , and performance modeling, and DevOps supporting the development of custom… more