- Broadcom (San Jose, CA)
- …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The day-to-day ... 1). Defining in the microarchitecture and implementing design of chip top level modules for L2/L3 Network Switching and...ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks,… more
- Capgemini (San Francisco, CA)
- …our business with semiconductor clients through comprehensive solutions in chip design, software, hardware, supply chain, and sustainability. Key Responsibilities: ... Job: Sales Organization: ERD PPL US Title: Sales Executive Semiconductor Chip Design Engineering Services Location: CA-Santa Clara Requisition ID: 082655 Other… more
- Northrop Grumman (Baltimore, MD)
- …and production support of state-of-the-art RF, digital, and mixed signal multi- chip modules (MCMs), Printed Wiring Boards (PWBs), and Circuit Card Assemblies ... (CCAs) using various substrate materials and chip -scale packaging technologies Collaboration within a cross-functional Integrated Product Team (IPT); effective and… more
- Broadcom (San Jose, CA)
- …node silicon (7nm, 5nm, 3nm and beyond). This role partners closely with chip design, system design, SI/PI, thermal, and manufacturing teams to define and deliver ... Key Responsibilities Package Architecture, Co-Design & Optimization Collaborate with chip design and analog/digital IP/PHY teams (224G/112G SerDes, PCIe Gen… more
- Microsoft Corporation (Santa Clara, CA)
- …and test plans. Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels. Drives the development of ... quantitative justification. Leads verification of correlation of system on chip (SoC) performance models to RTL implementation. Post-Silicon Validation Drives… more
- Twist BioScience (South San Francisco, CA)
- …mission is to close the loop. You will take the DNA from the chip , perform complex enzymology and library preparation, and analyze the sequencing data to prove ... (polymerases, ligases, nucleases, kinases) to repair, modify, and assemble DNA from chip to library.Execute NGS Library Prep: Select and run the appropriate library… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …role focuses on developing and integrating and validating high speed interface [Serdes, Chip 2 chip link] based subsystems in Emulation Platforms. Development ... verification environments, encompassing: System-level models including microcontrollers, memories, NoC (Network-on- Chip ), and high-speed communication interfaces Test case generation Interface… more
- Broadcom (Irvine, CA)
- …to independently develop test programs, including complex test flows to support chip specifications around performance and power consumption Must be able to support ... work with test hardware development teams, able to understand chip performance at ATE and contributions from the test...at ATE and contributions from the test hardware on chip behavior Experienced with extreme temperature testing of ASICs… more
- LinkedIn (Mountain View, CA)
- …Contribute to LinkedIn's liquid-cooling deployment strategy, assessing various direct-to- chip cooling technologies, comparing performance tradeoffs and operational ... such as phase imbalance, protection coordination, thermal irregularities, and liquid-to- chip cooling system failures. Basic Qualifications Bachelor's Degree in… more
- Oracle (Olympia, WA)
- …engineer or scientist to lead the deployment and management of direct-to- chip liquid cooling technology with our external manufacturing partners. The successful ... solutions. Responsibilities Key Responsibilities Serve as the technical lead for direct-to- chip liquid cooling systems with a focus on collaboration across external… more
- Meta (Sunnyvale, CA)
- …Responsibilities: Leverage Design Verification experience to build IP and System On Chip (SoC) and develop innovative ASIC solutions for data center applications. ... test benches with components for stimulus, checkers, and reference models Block/IP/SoC/full chip level verification Formal property verification or C vs RTL formal… more
- Oracle (Harrisburg, PA)
- …Working knowledge and design ability for data center direct-to- chip fluid cooling technologies, including using liquid-to-liquid, liquid-to-air, single-phase ... flow network modeling tools to generate data center digital twin models from chip to external heat rejection solutions. Design and conduct experiments for generating… more
- Meta (Austin, TX)
- …Silicon Validation Engineer, Reality Labs Responsibilities: Responsible for System on Chip and end-to-end system validation plan development, execution and sign-off ... teams (ie, architecture, Intellectual Property, Firmware, Electrical Engineering, System on Chip , and product engineer teams) to generate validation reports for SoC… more
- Apple (San Diego, CA)
- …part of a very dedicated team you will be at the heart of the chip design effort collaborating with all fields. Minimum Qualifications BS with 10+ years relevant ... of reusable verification framework. Knowledge of digital logic design, chip architecture and microarchitecture. Great teammate with excellent communication skills… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at… more
- RTX Corporation (Tewksbury, MA)
- …Fiber Channel. Background in FPGA hardware inference designs including SERDES, LVDS chip -to- chip and board-to-board. Understanding of allocating and flowing down ... requirements from the system to the component level. Knowledge of cost estimating, plus budget and schedule management. Experience working in a laboratory environment using logic analyzers, oscilloscopes, phase noise analyzer (PNA), and spectrum analyzer to… more
- Meta (Sunnyvale, CA)
- …GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications. Required Skills: ASIC Engineer, Physical ... physical design Preferred Qualifications: Preferred Qualifications Experience in full chip floor planning, partitioning, budgeting, and power grid planning… more
- Google (Sunnyvale, CA)
- …and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer, you will collaborate with Register-Transfer Level (RTL), ... Design for Testing (DFT), Floorplan, and full- chip Sign off teams. Additionally, you will solve technical problems with innovative micro-architecture and practical… more
- Teradyne (Irvine, CA)
- …and deployment of test solutions for Digital, High-Speed Digital, System on Chip , Mixed Signal and Analog semiconductor devices. Test program software development, ... Product engineering experience in Digital, High-Speed Digital, High-Power Computing, System on Chip , Mixed Signal, or Analog testing and test development on ATE… more
- Applied Materials (Santa Clara, CA)
- …global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service ... is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at… more
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