• Applied LLM Engineer, AI and Chip

    NVIDIA (Santa Clara, CA)
    …that's fueled by phenomenal technology-and outstanding people! As part of Nvidia's applied LLM chip design team, you will have the opportunity to tap into the ... unlimited potential of AI and change the landscape of chip design at Nvidia and throughout the industry. Our team operates at the intersection of research,… more
    NVIDIA (11/01/24)
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  • Senior C++ Software Engineer - Chip

    NVIDIA (Santa Clara, CA)
    …build and verification of architectural, rtl, and gate level designs. Our tools enable our chip design teams to work on state-of-art design technologies such ... software engineer, you will craft highly efficient software to automate and facilitate chip design and verification engineering workflows and processes, and look… more
    NVIDIA (09/04/24)
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  • Senior C++ Software Engineer - Chip

    NVIDIA (Santa Clara, CA)
    …a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be Doing: + Work as ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
    NVIDIA (10/13/24)
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  • Semiconductor Engineering Services Sales…

    Capgemini (San Francisco, CA)
    …highly motivated Semiconductor Engineering Services Sales Executive experienced in selling chip design services and product engineering services- software, ... track record of selling services to semiconductor companies. Experience selling chip design services and product engineering services- software, hardware… more
    Capgemini (10/03/24)
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  • Manager, Systems Development Engineering EDA…

    Google (Sunnyvale, CA)
    …experience with organizational design . Preferred qualifications: + Experience in EDA Tools/ Chip Design . + Experience interacting with the end users and ... practical experience. + 8 years of experience with system design . + 5 years of experience with managing technical...of Google-scale services. Come build things that matter. Electronic Design Automation (EDA) Cloud is a large, complex service… more
    Google (10/23/24)
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  • Chip Package Signal and Power Integrity…

    Google (Sunnyvale, CA)
    … and other SI/PI Engineers. You will work with various cross-functional teams, including Chip Design , System Design , software team and vendors. You will ... IO interfaces (serdes, memory, D2D) considering IO PHY, SI/PI and physical design . + Collaborate with chip design team, system design teams and suppliers… more
    Google (10/11/24)
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  • Chip Power Architecture Lead

    NVIDIA (Santa Clara, CA)
    …crowd: + Experience with a breadth of System Architectures in different areas of chip design and power management microarchitecture. + Inventions in one or more ... We are now looking for a Chip Power Architecture Lead! NVIDIA is seeking an exceptional Chip Power Architecture Lead to help us build power efficient and… more
    NVIDIA (08/28/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Electrical Engineering or equivalent experience + 5 plus years of proven experience in chip design , specializing in SOC integration and design automation. + ... + Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On- Chip design /integration flow, and design automation. + Strong coding… more
    NVIDIA (10/24/24)
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  • Staff RF/Analog Mixed-Signal IC Design

    Northrop Grumman (Linthicum, MD)
    …lead an IC design project from concept through tapeout. Create and maintain chip design schedule and meet tight deadlines in accordance with the overall ... and maintain a TS/SCI with polygraph security clearance. Preferred Qualifications: + Design chip lead with a proven record of successful tapeouts; ability to … more
    Northrop Grumman (11/02/24)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …years' experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and ... inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Improvement Technology Scaling to join our… more
    NVIDIA (11/01/24)
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  • Staff Digital Design Engineer

    Skyworks (Austin, TX)
    …for candidates with a BS + Strong motivation to contribute to all facets of chip design from conceptualization to release to mass production. + Working knowledge ... insertion), firmware development (some ICs include embedded processors), digital design verification, and full- chip mixed-signal verification. Responsibilities… more
    Skyworks (10/15/24)
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  • Timing Analog/Mixed Signal IC Design

    Skyworks (Nashua, NH)
    …related) Minimum Requirements * Strong motivation to contribute to all facets of chip design from conceptualization to release to mass production * Experience ... Timing Analog/Mixed Signal IC Design - Summer Intern 2025 Apply now "...blocks, do and/or supervise physical layout, verify circuit and chip -level operation and performance, and assist with tape-out related… more
    Skyworks (09/27/24)
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  • Digital Design - Summer Intern

    Skyworks (Austin, TX)
    …studies. Minimum Requirements: + Strong motivation to contribute to all facets of chip design from conceptualization to release to mass production. + Working ... insertion), firmware development (some ICs include embedded processors), digital design verification, and/or full- chip mixed-signal verification. Responsibilities… more
    Skyworks (09/20/24)
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  • Senior Physical Design Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …years experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and ... today! What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs....+ Participate in developing flow and tool methodologies for chip floorplan, power and clock distribution, chip more
    NVIDIA (08/08/24)
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  • Senior SOC Design Engineer

    NVIDIA (Santa Clara, CA)
    …and analyzing innovative microarchitectural structures and subsystems. Join the future of chip design , you will work on groundbreaking products with a ... gaming, and consumer use cases. + Collaborate with Architects, Chip Leads, and Customers on SOC IP design... Chip Leads, and Customers on SOC IP design , development, timing closure, power analysis, methodology alignment, and… more
    NVIDIA (10/22/24)
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  • Sr. Physical Design Engineer - Full…

    Amazon (San Diego, CA)
    …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part ... & Responsibilities: - Collaborate with architecture, timing, and logic design teams making a crucial impact on delivering cutting...shell and drive to automate flows - Proficiency in chip front-end and back-end implementation tools such as Fusion… more
    Amazon (10/08/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    …IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. * ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the … more
    Cisco (11/01/24)
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  • Sr. Staff Design Verification Engineer…

    Lightmatter (Mountain View, CA)
    …to join our team and help orchestrate the hardware engineering efforts on Lightmatter's chip design and tape-outs. In this job, you will work in constant ... Sr. Staff Design Verification Engineer Lightmatter is a photonic computer... and implement UVM testbenches for both subsystem-level and full- chip verification. This includes debugging testbenches, resolving issues, achieving… more
    Lightmatter (10/24/24)
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  • ASIC Design for Test Technical Leader

    Cisco (San Jose, CA)
    …IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. * ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the … more
    Cisco (08/16/24)
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  • Research Scientist, Design Automation - New…

    NVIDIA (Austin, TX)
    Design Automation research group is seeking leading researchers to work on AI for chip design and accelerated computing for EDA. You should have a strong ... software, machine learning (Graph, Generative AI, LLM, Agent) , and VLSI chip design methodology. Specific areas of research interest include but are not limited… more
    NVIDIA (10/29/24)
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