• Section Manager, Layout Design

    Skyworks (Newbury Park, CA)
    …of a larger layout group that also provides HBT, SAW and BAW Filters, SOI, CMOS and MCM layout services. In this position, you will have the opportunity to ... more
    Skyworks (02/15/25)
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  • Senior Analog Layout Engineer

    Capgemini (San Francisco, CA)
    …digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated ... more
    Capgemini (03/25/25)
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  • CAD Engineer

    NVIDIA (Santa Clara, CA)
    …plus year of work experience + A basic understanding of mosfet device behavior, CMOS layout , and VLSI design. + Excellent programming skills; experience with ... more
    NVIDIA (03/13/25)
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  • Electrical Engineering Intern - Santa Barbara

    Lockheed Martin (Goleta, CA)
    …simulations on circuit blocks for determining performance and optimizing designs\. Physical layout of CMOS circuit blocks for integration into higher level ... more
    Lockheed Martin (03/19/25)
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  • Sr./Principal HBM CAD Engineer - TPG

    Micron Technology, Inc. (Richardson, TX)
    …Familiarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND) + Knowledge of CMOS circuit design, layout and verification + Knowledge and experience ... more
    Micron Technology, Inc. (02/19/25)
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  • Senior Mask Layout Design Engineer

    NVIDIA (Santa Clara, CA)
    …of Photonics, CMOS , Electronics, and Systems engineers + Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ... more
    NVIDIA (02/13/25)
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  • CMOS Device Engineering, Dmts - TPG

    Micron Technology, Inc. (Boise, ID)
    …communicate and advance faster than ever. Drive the development of next generation CMOS devices employed in the most ground breaking Memory and Compute in Memory ... more
    Micron Technology, Inc. (03/08/25)
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  • CMOS Device Integration Engineer, MTS - TPG

    Micron Technology, Inc. (Boise, ID)
    …the world to learn, communicate and advance faster than ever. As an Advanced CMOS Device & Process Integration Engineer, you will play a crucial role in the ... more
    Micron Technology, Inc. (03/15/25)
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  • Senior Mask Layout Design Engineer

    NVIDIA (Santa Clara, CA)
    …integration would be excellent to have. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies + Validated experience with Cadence ... more
    NVIDIA (01/13/25)
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  • Sr. Director, Engineering

    Skyworks (Woburn, MA)
    …Amplifiers, PMU and Switching regulators + Advanced knowledge of device physics, CMOS fabrication processes, layout tradeoffs for high performance circuits + ... more
    Skyworks (04/02/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …LVS decks such as Dracula, Hercules, Calibre. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + Experience with analog ... more
    NVIDIA (03/06/25)
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  • Failure Analysis Engineer

    Power Integrations (San Jose, CA)
    …+ Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. Power Integrations is committed ... more
    Power Integrations (02/25/25)
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  • Staff Failure Analysis Engineer

    Power Integrations (San Jose, CA)
    …is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. + Verbal and reading, ... more
    Power Integrations (01/21/25)
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  • Senior Failure Analysis Engineer (Automotive)

    Power Integrations (San Jose, CA)
    …+ Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. Preferences will be given ... more
    Power Integrations (01/08/25)
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  • Integrated Circuit (IC) Layout and Mask…

    MIT Lincoln Laboratory (Lexington, MA)
    …(CCD) imagers, 193-nm lithography, fully depleted silicon-on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers, superconducting ... more
    MIT Lincoln Laboratory (03/12/25)
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  • Senior Photonic Layout Design Engineer

    NVIDIA (Santa Clara, CA)
    …Photonics, CMOS , Electronics, and Systems engineers + Conduct chip layout circuit design, circuit checking, and device evaluation and characterization. + ... more
    NVIDIA (01/30/25)
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  • Silicon IC Layout Designer

    Skyworks (Cedar Rapids, IA)
    Silicon IC Layout Designer Apply now " Date:Mar 10, 2025 Location: Cedar Rapids, IA, US Company: Skyworks If you are looking for a challenging and exciting career in ... more
    Skyworks (03/14/25)
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  • Analog Mixed Signal Layout Designer

    Broadcom (San Jose, CA)
    …developing and leading complex layout IC for high speed applications in advanced CMOS FinFET technologies such as 5nm and 3nm at the block level and chip level. ... more
    Broadcom (03/16/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …experience in Mask and Layout Design. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. + You are an authority with ... more
    NVIDIA (03/04/25)
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  • Failure Analysis Engineer

    Qualcomm (San Diego, CA)
    …experience . Hands on Scan/ATPG/MBIST debug . Sound theoretical knowledge of Digital/Analog CMOS circuits . Experience with CAD layout tools Hands on experience ... more
    Qualcomm (01/18/25)
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