• Integrated Circuit (IC) Layout

    MIT Lincoln Laboratory (Lexington, MA)
    …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... CurvyCore o Programming in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our exceptional career opportunities include… more
    MIT Lincoln Laboratory (09/12/24)
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  • Senior Mask Layout Design

    NVIDIA (Santa Clara, CA)
    Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone ... equivalent experience) + At least 5+ years of hands-on layout design experience + Deep understanding of...design experience + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. Validated… more
    NVIDIA (11/15/24)
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  • Senior Mask Layout Design

    NVIDIA (Santa Clara, CA)
    Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing ... MSEE is a plus. + 8+ years of relevant mask design / layout experience...excellent to have. + Deep understanding of analog circuit layout concepts in submicron CMOS technologies +… more
    NVIDIA (10/14/24)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using...(or equivalent experience) + Minimum of 6 years of mask design / layout experience… more
    NVIDIA (10/17/24)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …the world. This is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from ... you! We are looking for a Senior Mask Layout Design Engineer, someone... Design . + Deep understanding of analog circuit layout concepts in submicron CMOS technologies. +… more
    NVIDIA (09/04/24)
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  • Senior Mask Designer and CAD Engineer

    NVIDIA (Austin, TX)
    …creativity and intelligence. We would love to hear from you! We are seeking a Senior Mask Layout Design Engineer to join our growing and dynamic team. The ... equivalent experience) + 7+ years of industry experience in Mask and Layout Design . +...Layout Design . + Deep understanding of layout concepts in submicron CMOS technologies. +… more
    NVIDIA (09/27/24)
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  • ASIC/IC Layout Engineer

    Actalent (Morrisville, NC)
    … technology using custom IC design tools. Overview: We are looking for an experienced Mask Layout Design Engineer who is innovative and has a passion for ... IC Layout design of high-speed CMOS Interface D2D and SERDES for next generation Consumer & Cloud Computing Devices. The ideal candidate is a self-starter,… more
    Actalent (11/15/24)
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  • Senior/Principal Layout Designer - DRAM…

    Micron Technology, Inc. (Atlanta, GA)
    …DRAM Design group and our other engineering groups to apply multiple layout techniques to design and verify digital and analog circuits. Lastly, our ... teammate will be expected to understand various circuit design protocols, different fab processes, mask generation...Must have 10 + years of experience in analog layout designs in sophisticated CMOS processes. +… more
    Micron Technology, Inc. (09/03/24)
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  • Intern - Layout Designer

    Micron Technology, Inc. (Boise, ID)
    …communicate and advance faster than ever. As a Layout Designer in the DEG Layout Design group, you will create innovative layout to support Commodity, ... teams to build innovative layout , verify the layout working with Advanced Mask Development and...This feedback will be taken directly all through the design cycle leading to layout changes and… more
    Micron Technology, Inc. (09/09/24)
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  • Analog Layout Engineer

    Insight Global (St. Paul, MN)
    …the circuit design team. Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent performance, ... . Skills and Requirements 4+ years of Experience within Analog Layout Design Appropriate-level experience, knowledge, and scope of responsibility… more
    Insight Global (11/13/24)
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  • Principal/Sr. Principal Analog Mixed Signal IC…

    Northrop Grumman (Linthicum, MD)
    …experienced Integrated Circuit (IC) Layout Engineers to join our team in the design and layout of custom, low-power, analog and mixed signal circuits. The ... and physical measurement structures. Additional responsibilities involve floor planning, supporting design engineers, and coordination with mask team in reticle… more
    Northrop Grumman (11/09/24)
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  • Remote ASIC/IC Design Engineer

    Actalent (Morrisville, NC)
    …to help design and test great products! Overview: We are looking for an experienced Mask Layout Design Engineer who is innovative and has a passion for ... IC Layout design of high-speed CMOS Interface D2D and SERDES for next generation Consumer Cloud Computing Devices. The ideal candidate is a self-starter… more
    Actalent (11/14/24)
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  • Electronic-Photonic Process Design Kit…

    MIT Lincoln Laboratory (Lexington, MA)
    …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... changes. The engineer will collaborate with others involved in mask layout from basic layout ...o Programming in Perl, TCL, or Python o RF layout design experience o Experience with Cadence… more
    MIT Lincoln Laboratory (09/14/24)
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  • Hardware Design Engineer 1

    Actalent (Morrisville, NC)
    Overview: We are looking for an experienced Mask Layout Design Engineer who is innovative and has a passion for IC Layout design of high-speed ... layout of cutting edge high-performance high-speed low power CMOS Interface D2D and SERDES integrated circuits in foundry...TX OTAs LDO Clock Distribution Bandgap and Bias - Layout Design review presentations. - Layout more
    Actalent (11/15/24)
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  • Sr. Analog Design Lead - TPG

    Micron Technology, Inc. (San Jose, CA)
    …according to project timelines. + You will provide technical consultations on analog design and CMOS development, being a recognized Micron content expert and ... in pathfinding activities for upcoming projects or tech nodes, including CMOS scaling efforts, architecture definition, helping to solve sophisticated technical… more
    Micron Technology, Inc. (09/18/24)
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  • Senior Mixed-Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …mixed-signal circuits + Lead mask designers, provide mentorship for floorplan and layout design + Provide support to the lab characterization of silicon, and ... member of our Mixed-Signal team, you will be leading architecture definition and design of CMOS high-speed interface circuits and mixed-signal circuits. Strong… more
    NVIDIA (10/08/24)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …needle! As a member of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits. Strong hands-on ... and verification of mixed-signal circuits + Supervise closely IC circuit/ mask designers, provide floorplan and layout guidelines...lab characterization of silicon + Tackle challenges of circuit design in deep submicron CMOS + Take… more
    NVIDIA (09/12/24)
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  • ROIC Design Engineer

    Lockheed Martin (Goleta, CA)
    …digital to analog converters, and high speed serial transmitters * Transistor level layout mask design * Serial interface designs including serial ... Requirements and concept development of ROIC systems, circuit block design , circuit simulation, coordination of circuit layout ...Lab testing and debugging of hardware * Presentation of design review material * Coordination with CMOS more
    Lockheed Martin (10/02/24)
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  • CAD Engineer - TPG

    Micron Technology, Inc. (Atlanta, GA)
    …tape out and mask generation. + Drive close collaboration with DRAM design , layout , & verification methodology teams to propose and co-develop capabilities ... design preferred (DDR3/4/5, LP3/4/5, HBM, NAND) Knowledge of CMOS circuit design , layout and...Reliability flows such as HCI, BTI, EM/IR, crosstalk + Mask generation and tape out basics + Knowledge and… more
    Micron Technology, Inc. (09/20/24)
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  • SPF/Spice CAD Engineer - TPG

    Micron Technology, Inc. (Richardson, TX)
    …out and mask generation. + Drive close collaboration with DRAM design , layout , &verification methodology teams to propose and co-develop capabilities ... with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND). + Knowledge of CMOS circuit design , layout and verification. + CMOS transistor level … more
    Micron Technology, Inc. (10/25/24)
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