- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …Linac Coherent Light Source (LCLS) Directorate at SLAC is seeking a Control System Engineer to join the Engineering and Design controls team. The Control System ... Engineer will work on control system design , hardware deployment, system automation, and a suite of...triggers near the point of use, as well as CPU interrupts for software synchronization. The event timing… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …Linac Coherent Light Source (LCLS) Directorate at SLAC is seeking a Control System Engineer to join the Engineering and Design controls team. The Control System ... triggers near the point of use, as well as CPU interrupts for software synchronization. The event timing...jitter.** **As a member of the ECS Engineering and Design department, the Senior Control System Engineer … more
- NVIDIA (Hillsboro, OR)
- We are looking for a Senior CPU Design Engineer ! NVIDIA is seeking best-in-class CPU Design Engineers to design the world's leading CPUs. This ... team, you will be responsible for the micro-architecture, design and implementation of high-performance, low power CPU...the design is functional. + Exercise logic design skills to optimize and meet performance, timing… more
- Global Foundries (Richardson, TX)
- …insight, and passion to work to redefine what's possible Essential Responsibilities: As a CPU design engineer you own or participate in the following: ... information, visit www.gf.com. Summary of Role: We're seeking a CPU RTL design engineer with...and convergence of the block to project requirements (performance, timing , power, area, schedule) . Support of the verification… more
- NVIDIA (Santa Clara, CA)
- …aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts ... design requirements. + Engage with multiple teams and design the GPU or CPU clocks to...new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking… more
- NVIDIA (Santa Clara, CA)
- …aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts ... design requirements. + Engage with multiple teams and design the GPU or CPU clocks to...new Clocking topologies in RTL. + Collaborate with Physical design and timing team to evaluate Clocking… more
- NVIDIA (Santa Clara, CA)
- As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and ... timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility. This position...CPU team, you'll be a liaison between Logic design and Physical design teams responsible for… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...that in top level and deliver the fully verified, synthesis/ timing clean design + Work closely with… more
- Amazon (Cupertino, CA)
- … quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area and ... fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing , and back-end experts * Lead and Design to meet… more
- Meta (Sunnyvale, CA)
- …learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... development and debug 4. Collaboration with implementation team to close the design on timing and power **Minimum Qualifications:** Minimum Qualifications: 5.… more
- Meta (Sunnyvale, CA)
- …"Apply to Job" online on this web page. **Required Skills:** ASIC Design Engineer Responsibilities: 1. Responsible for micro-architecture development. 2. Perform ... debugging. 5. Collaborate with implementation team to close the design on timing and power. **Minimum Qualifications:**...and data path IPs 10. Experience in SoC Micro-architecture, Design and Integration 11. Experience in CPU ,… more
- Microsoft Corporation (Mountain View, CA)
- …Python OR equivalent experience. - 10+ years of relevant experience. - Expertise in CPU /SoC design principles. - For Front-End Handoff CAD Roles: - In-depth ... silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the development and adoption of cutting-edge...- Ability to design and verify reusable design components. - Expertise in Synthesis and Timing… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes + Develop flows...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Microsoft Corporation (Mountain View, CA)
- …engineers to help achieve that mission. We are looking for a **Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... (ASIC)/SOC designs. + 4+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon...Chip or Networking ASICs or Complex Control Logic + CPU or graphics core design . + Complex… more
- NVIDIA (Santa Clara, CA)
- …you can make a lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What you'll be doing: + Work in ... with architects, chip leads, and customers on SoC IP design , timing closure, power analysis, methodology alignment,...of relevant work experience in RTL development passionate about CPU , GPU, and HPC architectures. + Proven experience building… more
- NVIDIA (Santa Clara, CA)
- …this next wave of computing. We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling and Simulation to join our dynamic and growing ... significant and exciting role in improving the netlist and timing quality of our designs and if you are...What you'll be doing: + Participate in innovative Processor design in deep submicron technologies. + Work as part… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design -for-Test (DFT), Place & Route and Static Timing Analysis (STA).You ... of technology. Cadence is a pivotal leader in electronic design , building upon more than 30 years of computational...on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job… more
- NVIDIA (Santa Clara, CA)
- …measurement, Reset and Boot controllers. + You will be responsible for the RTL design , logic synthesis, and timing analysis of several modules. + Integrate ... is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has...including RTL design , asynchronous and synchronous Reset design , synthesis, timing analysis, and Spyglass/CDC/RDC checks… more
- Amazon (Cupertino, CA)
- …with Ethernet switching fabrics, Ethernet PHY and SerDes interfaces, embedded CPU subsytems, DDR2/DDR3/DDR4 memory design , network processors, I2C, USB ... Description AWS Infrastructure Services owns the design , planning, delivery, and operation of all AWS...areas of terabit switch fabrics, 10/40/100 gigabit interfaces, embedded CPU subsystems, and network processors. Previous experience in defining… more
- NVIDIA (Santa Clara, CA)
- …standard FPGA prototyping platforms. We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa Clara, CA. What you'll ... Build FPGA prototypes by making RTL FPGA-friendly, partitioning the design and taking it through synthesis and place and...and route. + Improve performance of the prototype, analyze timing and generate bit streams. + Bring up the… more
