- Qualcomm (Santa Clara, CA)
- …flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support ... more
- Qualcomm (San Diego, CA)
- …(ECO) flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance and tools/flows ... more
- NVIDIA (Santa Clara, CA)
- …to work in a dynamic team Ways to stand out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, ... more
- Qualcomm (Folsom, CA)
- …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Physical Design Clock Engineer, you will work with microarchitecture, RTL ... more
- Qualcomm (Boxborough, MA)
- … Design (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... more
- Google (Austin, TX)
- …Lead the collaboration with RTL, design verification, and physical design teams to develop an efficient CPU implementation. + Drive performance ... more
- Qualcomm (San Diego, CA)
- …Area:** Engineering Group, Engineering Group > SoC Architecture **General Summary:** As a CPU Performance and Power Analysis Engineer, you will be working on CPU ... more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 8 years of experience with physical design flow such as constraints, synthesis, floor planning, place and ... more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... more
- Qualcomm (San Diego, CA)
- …support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to ... more
- Qualcomm (San Diego, CA)
- …support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to ... more
- Broadcom (Fort Collins, CO)
- …strong technical hands-on competency in using leading edge physical design EDA tools in projects. + In-depth CPU /DSP architecture/algorithm working ... more
- Capgemini (Seattle, WA)
- **Job Role:** **SOC Design Verification Engineer** **Job location: Seattle WA** **Job Description:** We are looking for SOC Design Verification Engineer who can ... more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …of both small-scale and large-scale algorithms running on different computing systems ( CPU , GPU, ASIC, FPGA etc). These may include assessing the computing ... more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …of both small-scale and large-scale algorithms running on different computing systems ( CPU , GPU, ASIC, FPGA etc). These may include assessing the computing ... more
- Cisco (San Jose, CA)
- …meet timing and performance requirements. * Help define, evolve, and support our design methodology . * Collaborate with the verification team on as-needed basis ... more
- Siemens (Fremont, CA)
- …to build a career in a rapidly growing and constantly innovating Electronic Design Automation (EDA) industry? Do you enjoy working with cutting edge technology and ... more
- Qualcomm (San Diego, CA)
- …develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge ... more