- Qualcomm (Folsom, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... more
- Google (Mountain View, CA)
- … and power convergence. + Drive or develop physical design timing convergence tools and flows for advanced CPU designs to achieve outstanding Power ... more
- Qualcomm (San Diego, CA)
- …and implement multi-core CPU operations for all Qualcomm Business Units. As a CPU Physical Design Engineer, you will work with microarchitecture and RTL ... more
- Qualcomm (Santa Clara, CA)
- …to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support ... more
- Qualcomm (Austin, TX)
- …with CAD team to ensure proper and efficient model generation + Interacting with Physical Design team resolve memory PPA challenges + Depending on skill set, ... more
- Qualcomm (Boxborough, MA)
- … (micro-architecture, modeling, RTL), Implementation (synthesis & timing constraints), Design -for-Test (DFT), Physical Design (Place & route, CTS, ... more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... more
- Qualcomm (San Diego, CA)
- … closure (ECO) flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance and ... more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... more
- Qualcomm (San Diego, CA)
- …and develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading ... more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... more
- Cadence Design Systems, Inc. (Austin, TX)
- …verification and vPlans. Provide timely specification clarifications and debug support + Physical design deliverables. Create functional timing constraints, ... more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... more
- Qualcomm (San Diego, CA)
- …also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power ... more
- SpaceX (Irvine, CA)
- …integrates design blocks using Verilog/SystemVerilog and deliver a fully verified, synthesis/ timing clean design + Participate in all phases of ASIC and/or ... more
- NVIDIA (Westford, MA)
- …designers to deliver best in class IP + Partnering with our Physical Design team on partitioning, floorplanning and timing closure + Providing design ... more
- Broadcom (Fort Collins, CO)
- …strong technical hands-on competency in using leading edge physical design EDA tools in projects. + In-depth CPU /DSP architecture/algorithm working ... more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Chip, CPU Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for ... more
- Qualcomm (San Diego, CA)
- …embedded memory design flow: architecture, circuit design , physical implementation, compiler automation, characterization, timing and model generation + ... more