- Broadcom (Fort Collins, CO)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** DFT and STA Design Automation Senior Manager Broadcom ASIC Product Division is ... by relying on proven flows and methodology. As a Design Automation Senior Manager, you will lead...that own and provide the STA and DFT flows that enable our ASIC design … more
- Amazon (Austin, TX)
- …is possible today. Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to ... integrate DFT implementations * Work with physical design ...Perl, Python or Tcl - Experience with industry standard DFT /SCAN/ATPG tools - Experience with STA constraints… more
- Siemens (Austin, TX)
- …Expert About the role: Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world ... the increasingly complex world of chip, board, and system design . As a part of the Tessent team, you...Tessent team, you are responsible for developing and providing DFT solutions involving test IPs that improve the overall… more
- Capgemini (Santa Clara, CA)
- …pipeline design , interconnect and AMBA interfaces. + Candidate with design automation , scripting experience(Python) is preferrable". **Life at Capgemini** ... Santa Clara CA** **Job description:** We are seeking Digital Design (RTL) engineer for our full time role with...IP & PHY from 3rd parties). + Awareness of DFT concepts to be used to fix functional violation… more
- Cisco (San Jose, CA)
- …constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation , you excel at ... team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip...with Spyglass CDC and glitch analysis. * Experience with STA tools such as PrimeTime/Tempus. * Experience with scripting… more
- Belcan (Palo Alto, CA)
- …clock planning, bump placement / RDL routing, power grid generation, full chip STA timing, DFT strategy planning, and final physical verification. Good knowledge ... Sr. Physical Design Engineer Job Number: 354330 Category: Design...physical aware synthesis, floor planning, clock tree implementation, routing, STA timing signoff, and chip-finishing. Good knowledge of basic… more
- Meta (Sunnyvale, CA)
- … scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design Engineers, DV Engineers, ... with the Designers to create waivers. 6. Perform RTL DFT Analysis and improve the DFT coverage...Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- Meta (Austin, TX)
- … scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design Engineers, DV Engineers, ... with the Designers to create waivers. 6. Perform RTL DFT Analysis and improve the DFT coverage...Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC.… more
- Meta (Austin, TX)
- …blocks. 3. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks ... Gate Level Netlist for Timing, Area, Power. 6. Developing Automation scripts and Methodology for all FE-tools including (...scripts and Methodology for all FE-tools including ( Synthesis, STA ). 7. Work closely with the Design … more
- SpaceX (Sunnyvale, CA)
- …voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps ... submicron processes leakage/dynamic + Familiar with CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact… more
- Broadcom (San Jose, CA)
- …Expertise in micro-architecture design and PPA trade-offs. + Experience in synthesis, STA , and timing closure using tools like Synopsys DC or Cadence Genus. + ... AXI, AHB) and memory interfaces. + Understanding of low-power design techniques and DFT methodologies is a...Experience with scripting languages (eg, Python, Perl, TCL) for automation and design tool integration. + Familiarity… more
- Siemens (Wilsonville, OR)
- …Software Req ID: 450920 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world ... to 15 years. + Very good understanding of digital design and testing, Design -for-Test ( DFT )...synthesis, integrated circuit (IC) place and route, timing analysis ( STA ), logic equivalence checking, CDC and RDC We are… more
- Qualcomm (San Diego, CA)
- …ASIC/SoC design flows (micro-architecture, RTL design , verification, synthesis, timing/ STA , UPF, CLP, LEC formal verification, DFT , physical design .) ... and, ability to execute critical power analysis of critical design IPs for path to DDR. This is a...next Generation, high performance, low power Memory Subsystem RTL Design , flows and methodology for high performance ASICs in… more
- NVIDIA (Westford, MA)
- …equivalent experience) with 2 years experience in Synthesis and Timing. + Understanding of DFT logic and hands-on experience in design closure. + Expertise in ... and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing… more