• Principal Systems Design Engineer,…

    Micron Technology, Inc. (Folsom, CA)
    …physical verification and debug. + Experience supporting multiple tape-outs and working with memory design hierarchies. The US base salary range that Micron ... Layout and High-Speed I/O Design Engineer** to help shape the future of memory solutions for AI and high-performance computing. In this role, you will lead more
    Micron Technology, Inc. (11/20/25)
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  • Principal DRAM Architect - GPU Memory

    NVIDIA (Santa Clara, CA)
    …ECC/CRC, power management, and reliability optimization. + Lead innovation in high-speed memory interfaces, with deep expertise in HBM PHYs (wide I/O, TSV ... DRAM vendors and JEDEC working groups to influence global memory standards! Familiarity with HBM , GDDR, and...thermal behavior to guide architectural decisions. + Mentor engineers, lead technical reviews, and shape NVIDIA's long-term memory more
    NVIDIA (10/16/25)
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  • Hardware Engineering Technical Leader…

    Cisco (San Jose, CA)
    …Engineering, Computer Engineering, or related fields. * 8+ years experience in memory design /application OR Field Application Engineering. * Strong familiarity ... recommended and integrated into our solutions. Responsibilities * Collaborate with Cisco's design teams to enhance and improve memory reliability, availability,… more
    Cisco (11/12/25)
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  • Sr Principal Product Engineer - Memory IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …customer success. Position Overview Join our growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY IP products across a wide ... About Us Cadence is a pivotal leader in electronic design , building upon more than 30 years of computational...the development and support of high-performance IP related to memory protocols such as DDR, LPDDR, HBM ,… more
    Cadence Design Systems, Inc. (11/22/25)
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  • Principal Design Engineer, ASIC

    Micron Technology, Inc. (Richardson, TX)
    memory technologies. + Architect and model data path, control path, cache design , and IO interface logic for high-speed memory access and management. + ... (eg, DDR, LPDDR, ONFI, UCIe, PCIe, NVMe), and die-to-die communications modules. + Lead architecture reviews, contribute to design specifications, and guide RTL… more
    Micron Technology, Inc. (10/25/25)
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  • CMOS Device Integration Team - DMTS

    Micron Technology, Inc. (Boise, ID)
    …of CMOS device innovation, driving device and module development for future DRAM, HBM and emerging memory architectures. Your work will directly influence array ... for** **_all_** **.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into… more
    Micron Technology, Inc. (12/06/25)
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  • Lead Post-Silicon Validation Engineer

    NVIDIA (Santa Clara, CA)
    …and help lead post-silicon bringup, characterization, and productization of the memory system for NVIDIA's GPU products. + Develop, qualify, and work on ... We are seeking Lead Post-Silicon Validation Engineer within the GPU Engineering Team...compliance of memory system software and firmware. + You will be the… more
    NVIDIA (11/06/25)
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  • Interconnect Productization Lead

    Amazon (Cupertino, CA)
    …don't let it stop you from applying. Basic Qualifications - Proficiency in PCIe, Memory ( HBM , DDR), and other Interconnects. - 5+ YoE in developing silicon, SW/HW ... to build them with us! As an Interconnect Productization Lead , you will be responsible for ensuring the correct...of SoC architecture and interconnects. * Work with architecture, design , DV, SIPI and SW teams to verify and… more
    Amazon (10/28/25)
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  • ASIC Engineer, Infra Silicon Pre/Post Silicon…

    Meta (Austin, TX)
    …14. Experience with some of the following modules/domains: PCIe, Networking, Ethernet, Flash, Memory , CPU, GPU, DRAM (LP/DDR4/5 and/or HBM ) 15. Experience with ... reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization… more
    Meta (12/20/25)
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  • System Level Test & Diagnosis and SI Validation…

    Broadcom (Allentown, PA)
    …board)** + **System-level fault tolerance / redundancy** + **Familiarity with scan design , IJTAG, JTAG 1149.1, TDF/stuck-at testing, Memory BIST, IP testing** ... application, system and platform requirements to be able to lead and drive the necessary information gathering in the...modes, system state transitions during boot up (particularly for HBM based SIPs) - very desirable** + **SLT &… more
    Broadcom (10/30/25)
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