- MIT Lincoln Laboratory (Lexington, MA)
- …development, the Laboratory has implemented vertically integrated in-house resources to facilitate design , lithographic mask layout , material growth and ... and laying out devices, test structures, systems, and full mask reticles based on input from device and process...in Perl, TCL, or Python o Experience with RF layout design At MIT Lincoln Laboratory, our… more
- Northrop Grumman (Linthicum, MD)
- …for Principal IC Layout Engineer/Sr. Principal IC Layout Engineer: + Experience with hierarchical design , top-level floor-planning, and chip-level ... requirements. Strong communication skills are required. **This position can be filled at the Principal IC Layout Engineer OR the Sr. Principal IC Layout … more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... Amplifiers, and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies...(or equivalent experience) + Minimum of 6 years of mask design / layout experience… more
- Power Integrations (San Jose, CA)
- …interface. You will also work with IC layout designers in taping out physical layout design to mask shop. Requirements: + BS or MS in EE or Computer ... this position, you will be responsible for supporting all IC design CAD tools, which include but...limited to Cadence schematic entry, mixed mode circuit simulation, layout design , layout verification, logic… more
- NVIDIA (Santa Clara, CA)
- …simulation, and verification of mixed-signal circuits + Supervise closely IC circuit/ mask designers, provide floorplan and layout guidelines + Support lab ... of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits....and bring up. What you'll be doing: + Lead design and implementation of high speed interface circuit +… more
- Micron Technology, Inc. (Atlanta, GA)
- …and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design , custom layout , parameterized cells, automated ... mask generation. + Drive close collaboration with DRAM design , layout , & verification methodology teams to...+ Experience developing software prototypes for innovative ideas in IC design , layout , and analysis… more
- Renesas (Austin, TX)
- …+ Oversee the work of mask layout staff + Write design specifications, IC verification and validation plans + Participate in test specification ... specs for power, speed and area + Oversee the work of mask layout staff + Write design specifications, IC verification and validation plans + Participate… more
- Cisco (Holmdel, NJ)
- …or equivalent in optical engineering, physics, electrical engineering. * 5+ years of photonic IC design experience in industry. * 5+ years of experience with ... dynamic group that develops advanced photonics chips for optical communications products. You will design , simulate, layout and test PIC's. You will design ,… more
- Northrop Grumman (Linthicum, MD)
- …engineering. ATL is responsible for all aspects of semiconductor technology including design , mask making, wafer fabrication, test, and assembly. The candidate ... architect role in the development and execution of mixed-signal/RF IC device test solutions for products in various fab...hardware skills including probe card and package part fixture/DIB design & coordinating layout & assembly +… more
- Micron Technology, Inc. (Dallas, TX)
- …and flows enable all aspects of mixed-signal, transistor-level custom IC design including logical design , custom layout , parameterized cells, automated ... place and route tools, physical design verification (LVS, DRC), ERC, Layout Parasitic...mask generation. + Drive close collaboration with DRAM design , layout , &verification methodology teams to propose… more
- NY CREATES (Albany, NY)
- …of photonic devices, specifically silicon or III-V photonics. + Familiarity with PIC/ IC layout and verification tools (KLayout, Lumerical, Ansys, Cadence, Mentor ... new technologies in a 300 mm CMOS line. + Design of experiments - understanding of photonics and how...test data + Coordinating with vendors such as the mask house, dicing/packaging, and any outsourced processes. + Process/measurement… more
- NY CREATES (Albany, NY)
- …of photonic devices, specifically silicon or III-V photonics + Familiarity with IC layout and verification tools (KLayout, Cadence, Mentor Graphics, Synopsys) ... but are not limited to: + Handling 3rd party design IP. + Design rule checking and...team members. + Coordinating with vendors such as the mask house, dicing/packaging, and any outsourced processes + Integration… more
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