- Qualcomm (San Diego, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Siemens (Austin, TX)
- …candidate should have very good knowledge of Tcl/Python programming, digital circuit design , and design implementation flows with particular emphasis ... Job Family: Software Req ID: 457349 Title: Timing Analyst ( STA ) Expert About the...+ Knowledge and understanding of all aspects of a design flow - particularly SDC, static timing … more
- Cisco (San Jose, CA)
- …or MS Degree in Electrical or Computer Engineering with 10 Years Experience with ASIC design timing closure flow ( STA ) and methodology. * Hands-on experience ... timing and routing congestion issues, influencing key design and physical implementation decisions early in...constraints generation and validation, clock domain crossing checks, and timing closure. * Expertise in STA tools… more
- Cadence Design Systems, Inc. (Cary, NC)
- …physical design implementation , including floor planning, power grid design , place and route, clock tree synthesis, timing closure, power/signal ... of challenging designs, ie low power and high speed design . As well as participating in or leading next...LVS, ANT, ERC etc. - Deep experience of static timing analysis - Ability to learn quickly - High… more
- SpaceX (Irvine, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA / Timing Engineer/Level I: $120,000.00 - $145,000.00/per year ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer...Physical Design STA / Timing Engineer/Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power intent ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In… more
- Qualcomm (Folsom, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Meta (Austin, TX)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... scripts and Methodology for all FE-tools including ( Synthesis, STA ). 7. Work closely with the Design ...them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing /congestion… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power...including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation .… more
- Meta (Sunnyvale, CA)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design...them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Meta (Austin, TX)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design...them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Belcan (Palo Alto, CA)
- …physical design , including physical aware synthesis, floor planning, clock tree implementation , routing, STA timing signoff, and chip-finishing. Good ... placement / RDL routing, power grid generation, full chip STA timing , DFT strategy planning, and final...verification Working knowledge of UPF specification in Power Intent design , implementation , and verification of power gating,… more
- Cisco (San Jose, CA)
- …STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and ... to understand chip architecture and guide them in refining design and timing constraints for seamless physical...or related experience. * Experience with microarchitecture and RTL implementation . * Experience with digital design concepts… more
- Amazon (Redmond, WA)
- …to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC ... equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis, STA and working with...Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical design .… more
- Capgemini (Santa Clara, CA)
- …for Lint/CDC issues, checking synthesizability and timing quality of the design , checking low power implementation , supporting verification team with debug ... specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA...and support physical design teams on … more
- Google (Mountain View, CA)
- …distribution, chip assembly and P&R, timing closure. + Develop physical design methodologies and automation scripts for various implementation steps. + ... Drive architectural feasibility studies, explore RTL/ design tradeoffs for physical design closure. + Perform block level physical implementation steps… more
- Broadcom (San Jose, CA)
- …Expertise in micro-architecture design and PPA trade-offs. + Experience in synthesis, STA , and timing closure using tools like Synopsys DC or Cadence Genus. ... a Staff Digital Front-End Designer, you will own the design and implementation of complex digital IP...You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing … more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- NVIDIA (Santa Clara, CA)
- …logic synthesis, netlist quality checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation and ... understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure. + Experience in...and/or flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
- MetaOption, LLC (Milpitas, CA)
- … Design Engineer with 8-10 years of experience in pre-silicon validation, implementation , CAD, and block-level design . The ideal candidate will have strong ... teams to ensure successful ASIC tapeouts. Key Responsibilities: o Perform pre-layout Static Timing Analysis ( STA ) to validate feasibility and timing … more