- Cadence Design Systems, Inc. (San Jose, CA)
- …the Design IP Group. The candidate must have solid, hands-on experience in mixed - signal IP design and/or SoC development with a history in successfully ... more
- Teledyne (Camarillo, CA)
- …to the next level with us** ! Teledyne Imaging Sensors is looking for a ** Senior Analog Mixed Signal IC Design engineer** responsible for supporting the ... more
- Cadence Design Systems, Inc. (San Jose, CA)
- …logic and debug skills. Engineering expertise in mixed - signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly ... more
- Cadence Design Systems, Inc. (San Jose, CA)
- …dynamic IP team and help lead the development of best in class digital and mixed signal IP and subsystem products. This is a tremendous opportunity to ... more
- The Boeing Company (Huntington Beach, CA)
- …(Verilog, VHDL), + RTL verification (simulation, emulation), + Integration of 3rd party IP (digital, mixed - signal ), synthesis, place & route, design-for-test ... more
- Northrop Grumman (Linthicum, MD)
- …have a technical lead/test architect role in the development and execution of mixed - signal /RF IC device test solutions for products in various fab technologies ... more
- Teradyne (Westlake Village, CA)
- …This position will collaborate with semiconductor technologists to explore and propose mixed - signal concepts in response to strategic direction from Teradyne's ... more
- Capgemini (San Jose, CA)
- …running Lint In checks, Spyglass CDC RDC. They will be managing Analog blocks and mixed signal blocks and especially involved in using the Analog to Digital ... more
- CACI International (Los Gatos, CA)
- …from concept through system test and release + Expertise developing firmware for complex mixed signal environments (equal parts analog and high speed digital) + ... more
- Micron Technology, Inc. (Atlanta, GA)
- …or a Bachelors degree with 4+ years of experience in pre-silicon RTL design, Mixed - signal design plus the following: + In-depth knowledge of ASIC design flow ... more
- SpaceX (Irvine, CA)
- …clock domain crossing paths at block and full chip level + Work with mixed signal IP /PLL/SerDes/PHY teams to drive integration, timing, logical equivalence ... more