• Memory System Designer and Place

    Broadcom (Mendota Heights, MN)
    …+ Architect and design memory subsystems + Implement RTL of subsystem designs + Place and route (physical design) + Design closure: timing, DRC, LVS, EM/IR, ... more
    Broadcom (02/25/25)
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  • Member of Technical Staff Physical Design - PnR…

    onsemi (Richardson, TX)
    …candidates a positive recruitment experience that builds our brand as a great place to work. **onsemi** is an Equal Opportunity and Affirmative Action employer. The ... more
    onsemi (03/27/25)
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  • P&R CAD Senior Staff Engineer

    Qualcomm (San Diego, CA)
    …solutions for the Snapdragon chips powering billions of mobile devices. The position requires Place and Route experience and CAD development skills to define and ... more
    Qualcomm (02/21/25)
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  • Sr. Staff CPU Physical Design CAD Engineer

    Qualcomm (Santa Clara, CA)
    …+ Develop, integrate and release new features in our high-performance place -and- route CAD flow + Architect and recommend methodology improvements ... more
    Qualcomm (03/06/25)
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  • Product Engineer - FPGA Rtl Synthesis

    Siemens (Fremont, CA)
    …Synthesis solutions. College-level exposure to FPGA hardware design through RTL Synthesis and Place & Route is key. AMD/Xilinx or Intel/Altera, Lattice, or ... more
    Siemens (04/18/25)
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  • Sr/Principal Engineer: FPGA/ASIC Engineer - Dulles…

    Northrop Grumman (Dulles, VA)
    …analysis and systems architecture, design, coding, test bench design, verification, synthesis and place , & route for our Command and Data Handling (CD&H) ... more
    Northrop Grumman (04/08/25)
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  • CPU Physical Design Engineer

    Qualcomm (San Diego, CA)
    …of library cells and optimizations. + Solid understanding industry standard tools for synthesis, place & route and tapeout flows. + Experience with Synthesis, ... more
    Qualcomm (04/01/25)
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  • Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …physical implementation through synthesis, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, ... more
    Amazon (03/19/25)
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  • Sr. Principal STA/PD Solutions Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …bug fixes. Work on various aspects of physical design including timing analysis, place and route , extraction, spice etc. Job Responsibilities: . Perform Static ... more
    Cadence Design Systems, Inc. (03/12/25)
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  • Sr. Physical Design Engineer, Annapurna Labs

    Amazon (Austin, TX)
    …physical implementation through synthesis, floor planning, bus / pin planning, place and route , power/clock distribution, congestion analysis, timing closure, ... more
    Amazon (03/04/25)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route , clock tree synthesis, static timing ... more
    Meta (04/15/25)
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  • Software Architect - FPGA Emulation/Prototyping…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Emulation/Prototyping guru + Experience working on delivery of EDA applications (synthesis/ place / route /timing/optimizations). + Expert in Timing & Clocking of ... more
    Cadence Design Systems, Inc. (04/09/25)
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  • CPU Physical Design Pathfinding Engineer

    Qualcomm (San Diego, CA)
    …Power, Area and Performance goals. Must have skill/experience + Experience with Synthesis, place and route and signoff timing/power analysis. + Knowledge of high ... more
    Qualcomm (04/03/25)
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  • Physical Design Engineer - Staff

    Qualcomm (Austin, TX)
    …role involves good understanding of functional and test (DFT) mode constraints for place and route , floorplanning, power planning, IR drop analysis, cell ... more
    Qualcomm (03/28/25)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route , clock tree synthesis, static timing ... more
    Meta (01/21/25)
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  • Senior Physical Design Applications Engineer…

    Cadence Design Systems, Inc. (San Jose, CA)
    …teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: ... more
    Cadence Design Systems, Inc. (04/02/25)
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  • R&D Engineer IC Design

    Broadcom (San Jose, CA)
    …circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route , and timing and power use. Analyzes equipment to ... more
    Broadcom (04/15/25)
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  • ASIC Physical Design Engineer Intern, Annapurna…

    Amazon (Cupertino, CA)
    …design: full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route , power integrity analysis, and physical ... more
    Amazon (04/04/25)
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  • Application Engineer Architect

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route , Design Closure, and timing/power signoff + Guide customers ... more
    Cadence Design Systems, Inc. (03/31/25)
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  • Aprisa Account Technology Manager (ATM)

    Siemens (Austin, TX)
    …growth area for Siemens EDA in the sales deployment of a successful technology - Aprisa Place and Route - recently acquired by Siemens. This is a product poised ... more
    Siemens (03/04/25)
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