• Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …in advanced nodes and their impact on DRC closure and PPA optimization + Understanding of power intent files such as UPF , and use of FSDB/SAIFs for power ... of GPU, CPU and SOCs, with emphasis on PPA ( Power , Performance, Area) and runtime improvement of the physical...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
    NVIDIA (11/19/25)
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  • ASIC Engineer , Physical Design

    Meta (Sunnyvale, CA)
    power grid planning 19. Experience with low power implementation, power gating, multiple voltage rails, UPF /CPF knowledge 20. Experience in planning, ... methodology , and advanced packaging 25. Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC **Public Compensation:**… more
    Meta (11/05/25)
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  • Senior Engineer , Front End Computer Aided…

    Microsoft Corporation (Mountain View, CA)
    …to tools Timevision, Fishtail, Formality/LEC, Genus, Fusion Compile. - Expertise in RTL power / UPF linting flows like Power Artist/Jules, VCLP. - Expertise ... curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and… more
    Microsoft Corporation (12/03/25)
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  • Physical Verification Engineer (ASIC…

    ManpowerGroup (Phoenix, AZ)
    …Experience (Nice to Have)** + Experience with **multi-voltage designs** and **low- power verification** ( UPF /CPF). + Familiarity with **DFM (Design for ... **Job Title: Physical Verification Engineer (ASIC Design)** **Location: USA & Canada (Remote...and final report generation. + Collaborate with CAD and methodology teams to refine verification flows and integrate new… more
    ManpowerGroup (11/14/25)
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  • Senior ASIC Engineer , IP Design, Silicon

    Google (San Diego, CA)
    …simulations. + Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. + Participate in synthesis, timing/ power estimation and ... Senior ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain...Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology . **Preferred qualifications:** + Master's degree or PhD in… more
    Google (12/06/25)
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  • Principal SoC Design Verification Engineer

    Global Foundries (Richardson, TX)
    …the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Summary of ... Role: Seeking a Senior System-on-Chip Design Verification engineer to verify the High-Performance Data Processing Unit Chiplets and Automotive Microcontrollers . The… more
    Global Foundries (12/12/25)
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