- Cadence Design Systems, Inc. (San Jose, CA)
- …and methodologies. . Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing , Distributed and Concurrent STA flows. . Work efficiently with R&D ... impact on the world of technology. Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool....and customer to enable various timing analysis & ECO flows including newer advanced technologies.… more
- Renesas (Duluth, GA)
- Principal Digital Design Engineer Job Description + Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit + Contribute as ... verification reviews + Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking + Create documentation targeting… more
- Insight Global (Beaverton, OR)
- Job Description Job Description: One of our Semiconductor clients is seeking a Principal Mixed Signal Design Engineer to lead the development of cutting-edge ... Digital Design: Familiarity with automated digital design tools and processes, including Verilog, synthesis, place & route, and static timing analysis ( STA ). more
- Cadence Design Systems, Inc. (San Jose, CA)
- …for high-performance memory IP architecture design, owning the IC micro-architecture, timing budget, power analysis platform development. + Proficiency in logic ... design, simulation, synthesis, STA and testing + Proficiency in Verilog/SystemVerilog and its simulation environment + Good knowledge of IC design for high-speed and… more