- Fortive Corporation (Beaverton, OR)
- Job Title: Senior ASIC CAD Engineer Job Description: We are seeking an experienced and detail-oriented Senior CAD Engineer to join our team. ... to create, modify, and maintain an intuitive and automated ASIC design environment. This role will also require extensive...collaboratively. + Strong communication and team management skills. This Senior CAD Engineer role provides… more
- Palo Alto Networks (Santa Clara, CA)
- …goal is to create an environment where we all win with precision. **Your Career** As an ASIC Integration and CAD Engineer , you will ensure that the ASICs in ... resets, and synchronization. You will collaborate closely with the ASIC vendor and the PANW ASIC design...with the ASIC vendor and the PANW ASIC design team in floorplanning, closing timing, validating constraints,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...Verilog, System Verilog or similar HVL + Experience with CAD and physical design methodologies (flow and tool development),… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers ... including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and using the latest process technologies. What we need… more
- NVIDIA (Santa Clara, CA)
- …team, you'll design, develop and support sophisticated flows around EDA tools and our CAD programs. What you'll be doing: + You will architect highly automated and ... Be responsible for design, implementation and testing in-house of CAD programs + Work with design teams and leading...design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams… more
- Amazon (Austin, TX)
- …Europe, Singapore, and Japan, and customers across all industries. We are seeking experienced Senior Substrate CAD layout Engineer for the next generation of ... and want to reach beyond what is possible today. As a Substrate/PCB layout engineer you will participate in the definition and implementation of substrate and PCB… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... flow, and tool for high-speed designs, with focus on CAD and automation. + Develop custom flows for validating...Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling… more
- NVIDIA (Santa Clara, CA)
- …in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the ... Layout team, you will collaborate to implement high speed/density ASIC packages. + Perform substrate breakout patterns for ...size, cost, and system performance. + Develop symbols and CAD library databases using Cadence APD design tools +… more
- NVIDIA (Santa Clara, CA)
- …to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip ... Are you looking for an SOC Design Engineer opportunity? If yes, come and join us....GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design, CAD , Package Design, Software,… more
- University of Southern California (Arlington, VA)
- Senior Research Engineer IApply (https://usc.wd5.myworkdayjobs.com/ExternalUSCCareers/job/Arlington-VA/ Senior -Research- Engineer -I\_REQ20140783/apply) ... leader in disrupting and advancing the fields of front-end ASIC and FPGA design, reconfigurable architectures, and EDA tools....to perform research and development in the area of CAD and EDA tools for FPGA hardware. This position… more
- L3Harris (Anaheim, CA)
- Job Title: GPS Senior Specialist, Electrical Engineer Job Code: 19588 Job Location: Anaheim, CA (Vermont Ave. IEC) Job Schedule: 4/10 Work Schedule Job ... Description: As a Sr. Specialist Electrical Engineer , the candidate must have experience with L band...and flow down applicable requirements to other groups (software, ASIC , & test) so that they can contribute to… more
- Cisco (San Jose, CA)
- …Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. ... flows, and post-silicon test bring up procedures. Preferred Qualifications: * DFT CAD development - Test Architecture, Methodology and Infrastructure * Post silicon… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... Define, develop and deploy innovative physical design methodologies (RTL2GDS) and CAD flows for ML Accelerator chips in advanced nodes Drive improvement… more
- SpaceX (Irvine, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your ... Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX...cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind,...3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm,… more
- Leidos (San Diego, CA)
- **Description** The Leidos Innovations Center has an immediate opening for a mid-level **FPGA Engineer ** to work in San Diego, CA. This is an exciting opportunity to ... determine root cause of test failures, and iterate with senior staff to determine design changes to improve FPGA...including FPGA designs and system integration and testing with CAD and lab activities. + Collaborate in scientific research,… more
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