- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. ... more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and ... more
- The Boeing Company (Kent, WA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... more
- The Boeing Company (Tukwila, WA)
- …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... more
- Palo Alto Networks (Santa Clara, CA)
- …meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize ... more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... more
- Cisco (San Jose, CA)
- …to address design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, ... more
- SpaceX (Irvine, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $160,000.00 - $220,000.00/per year Your ... more
- Broadcom (Irvine, CA)
- … engineer capable of leading external and internal cross-functional teams in areas such as physical design , STA, DFT, and packaging? Have you taped out so many ... more
- Cisco (San Jose, CA)
- …verification team to achieve coverage closure. * Collaborate with the verification and physical design teams to resolve block level issues. * Perform diagnostic ... more
- Amazon (San Diego, CA)
- …of Silicon development from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring up, test, characterization, ... more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... more
- SpaceX (Irvine, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is seeking an outstanding Senior ASIC Power Integrity Engineer who is dedicated to collaborating ... more
- NVIDIA (Westford, MA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... more
- Cisco (San Jose, CA)
- …and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. *Additionally, you'll develop methodologies, ... more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... more