• Senior ASIC Physical

    Capgemini (Santa Clara, CA)
    **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
    Capgemini (01/15/25)
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  • Senior ASIC Physical

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. ... inventiveness and intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for high-performance designs, eg… more
    NVIDIA (01/08/25)
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  • Senior ASIC Physical

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster… more
    NVIDIA (12/25/24)
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  • Senior E/E & Semiconductor Engineer…

    Capgemini (San Francisco, CA)
    ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
    Capgemini (01/15/25)
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  • ASIC /FPGA Design and Verification…

    The Boeing Company (El Segundo, CA)
    …and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) + Integrate ... & Weapons Systems has an exciting opportunity for an ** ASIC and/or FPGA Design and Verification Engineer** **(Experienced, Lead or Senior )** to join us as… more
    The Boeing Company (01/24/25)
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  • Senior ASIC Floorplan Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and … more
    NVIDIA (11/06/24)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 -… more
    SpaceX (11/15/24)
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  • Senior ASIC Design

    Cisco (San Jose, CA)
    …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation… more
    Cisco (01/24/25)
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  • ASIC Design Engineer, Senior

    Cisco (San Jose, CA)
    …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... * Bachelor's degree in Electrical or Computer engineering and 12+ years of ASIC Design experience. * Verilog/System Verilog programming experience. * Interactive… more
    Cisco (01/15/25)
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  • Senior ASIC Design Engineer

    Cisco (San Jose, CA)
    …to address design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, ... Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering with 4+… more
    Cisco (01/11/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design more
    NVIDIA (11/05/24)
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  • Senior ASIC Design Engineer…

    NVIDIA (Santa Clara, CA)
    …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the… more
    NVIDIA (01/21/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …+ As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks. + You ... today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is...SOC clocking. The team collaborates with the front end design team to understand the clocking requirements for the… more
    NVIDIA (01/21/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $160,000.00 - $220,000.00/per year Your ... Sr. ASIC Design Engineer (Silicon Engineering) at...age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants… more
    SpaceX (11/16/24)
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  • Senior ASIC Integration and CAD…

    Palo Alto Networks (Santa Clara, CA)
    …You will collaborate closely with the ASIC vendor and the PANW ASIC design team in floorplanning, closing timing, validating constraints, and optimizing ... RAMs, CAMs, custom IPs, and IO pads throughout the design hierarchy + Collaborate with external ASIC ...+ RTL quality checks: Lint, CDC, RDC, X-verification + Physical design for networking ASICs with wide… more
    Palo Alto Networks (12/21/24)
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  • Senior ASIC Designer

    Western Digital (Roseville, CA)
    …thing in data. **Job Description** We are seeking a highly skilled and experienced Senior ASIC Designer to join our engineering team. The ideal candidate will ... design , with extensive Verilog coding experience, and a good understanding of physical design . This role involves designing, developing, and optimizing ASICs… more
    Western Digital (11/16/24)
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  • Sr. ASIC Design Verification…

    SpaceX (Irvine, CA)
    Sr. ASIC Design Verification Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (01/16/25)
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  • Sr. Technical Program Manager, ASIC

    Amazon (Redmond, WA)
    …of Silicon development from architecture definition, RTL design , Verification, IP design , Physical design , silicon bring up, test, characterization, ... ASIC /SOC leads) to create project execution plans for ASIC /SOC development considering all criteria to design ...used to drive multi-million dollar businesses and reporting to senior leadership Amazon is committed to a diverse and… more
    Amazon (01/22/25)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
    NVIDIA (01/22/25)
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  • Sr. SOC/ ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +...design and timing closure + Deep understanding of ASIC design flow, top-down and bottom-up … more
    SpaceX (11/22/24)
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