• Senior Clocks Methodology

    NVIDIA (Santa Clara, CA)
    …us today. The NVIDIA Clocks group is looking for a top ASIC Methodology engineer with proven experience in high-speed logic design and verification. In order ... has increased significantly. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints. What… more
    NVIDIA (10/22/24)
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  • Senior DFT Methodology

    NVIDIA (Santa Clara, CA)
    …imagination and intelligence. Make the choice to join us today. DFX Methodology Group at NVIDIA works on groundbreaking innovations involving crafting creative ... + Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power. + Experience in...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
    NVIDIA (08/28/24)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and/or full chip level. + Work with PD, DFX, Clocks , and other teams in coming up with timing...experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS… more
    NVIDIA (09/20/24)
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