- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... an ideal role. What You'll Be Doing: + Develop Timing sign-off flows, constraints and QOR metrics for custom...using standard cells and custom designs. + Validating the timing of custom circuit design using NanoTime and various… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- SpaceX (Irvine, CA)
- Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Improvement ... running chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design… more
- NVIDIA (Santa Clara, CA)
- …for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across ... + Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Familiar with various process related design… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, ... experience across the complete ASIC/SOC design flow including routing, static timing closure, EM/IR analysis and chip finishing.** **Job Responsibility:** *Chip… more
- Microsoft Corporation (Mountain View, CA)
- …contributing to the future of Artificial Intelligence and Computing. We are looking for a ** Senior Silicon Engineer ** to join our team! If you are like tackling ... UPF (Unified Power Format)/Low Power methodology /architecture, DFT methodology , Synthesis, Place and Route and Extracted Timing... methodology , Synthesis, Place and Route and Extracted Timing model generation in Timing Analysis tools… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... partitioning, timing budget generation, power planning, top-level PnR, CTS, block...from netlist to GDS + Understanding SI prevention, fixing methodology and implementation + Proficient in layout edit techniques… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for the ... blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. . Static and...Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and external teams… more
- Cisco (San Jose, CA)
- …hardware solutions. What You'll Do * Be part of the development organization as an Senior ASIC Design Engineer with primary focus on RTL Design. * Create ... specifications and participate in reviews. * Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design… more
- NVIDIA (Westford, MA)
- …improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our DPUs and SOCs ... equivalent experience) with 4 years experience in Synthesis and Timing . + Expertise in Static Timing Analysis...Synthesis and Timing . + Expertise in Static Timing Analysis (STA), Clock-Domain Crossing (CDC), and Reset Domain… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. * Contribute to full chip integration and timing methodology /analysis. * Develop and analyze functional coverage. * Help ... define, evolve, and support our design methodology . * Collaborate with the verification team to address...closely with the physical design team to close design timing and place-and-route issues. * Triage, debug, and root… more
- The Boeing Company (Huntington Beach, CA)
- …of these projects. We are seeking a **Digital Integrated Circuit Design Engineer (Mid-Level, Senior or Lead)** with experience developing complex, ... (digital, mixed-signal), synthesis, place & route, design-for-test (DFT) insertion + Static timing analysis / timing closure + Power analysis, formal… more
- Microsoft Corporation (Austin, TX)
- …Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial ... Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc. + Timing closure of high-performance digital Intellectual Property (IP) + Silicon validation +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more