• Lead AE in Digital and STA

    Cadence Design Systems, Inc. (Moylan, MN)
    …the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware , and intellectual property to ... ResponsibilitiesThis is an excellent opportunity to work on challenging and complex SoC projects at advanced technology nodes with leading companies in the… more
    Cadence Design Systems, Inc. (12/11/25)
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  • SoC Physical Design Engineer

    Google (Sunnyvale, CA)
    SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior ... such as synthesis, place and route, Static Timing Analysis ( STA ), verification, or power analysis. **Preferred qualifications:** + Master's...complex SoC . + Experience with multiple-cycles of SoC in ASIC design . + Experience with… more
    Google (12/11/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    …tests in C for custom hardware 5. Help create and maintain design documentation including IP/ SoC Micro Architecture document (collaborator/owner), IP/ SoC ... with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4....practical experience 7. 6+ years of experience in digital design , hardware engineering or related experience 8.… more
    Meta (12/08/25)
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  • Staff Static Timing Analysis Lead, Cloud

    Google (Sunnyvale, CA)
    …Timing Analysis. + 5 years of experience in leading STA activities for SOC . + Experience in extraction of design parameters, QoR metrics, and analyzing data ... experience. + 8 years of experience with Static Timing Analysis ( STA ) activities, including project planning, scheduling, task allocation, and progress tracking… more
    Google (12/04/25)
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  • Sr Advanced FPGA Design Engineer

    Honeywell (Phoenix, AZ)
    …and engagement, and fostering an inclusive culture. **KEY RESPONSIBILITIES** + VHDL, DSP, and STA knowledge + Xilinx FPGA design and development + IC experience ... As a Sr Advanced Semiconductor FPGA Design Engineer here at Honeywell, you will play...VALUE** + Professional knowledge of the DO-254 Airborne Electronic Hardware development lifecycle + Professional knowledge of VHDL or… more
    Honeywell (10/16/25)
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  • Sr. Specialist, Electrical Engineer (ASIC / FPGA…

    L3Harris (Herndon, VA)
    …Clearance. + Proficiency in mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs. + Proficient in VHDL ... of national security. Job Title: Sr. Specialist ASIC/FPGA Senior Design Engineer Job Code: 30428 Job Location: Herndon, VA...+ Generate test plans. + Perform module level verification, synthesis/ STA , Lab debug, SW driven validation on Linux based… more
    L3Harris (10/26/25)
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  • ASIC/FPGA Design Engineer (SMES)

    L3Harris (Camden, NJ)
    …products. + Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs. + Proficient with CDC, RDC. ... in the interest of national security. Job Title: ASIC/FPGA Design Engineer (SMES) Job Code: 29446 Job Location: Camden,...+ Generate test plans + Perform module level verification, synthesis/ STA , Lab debug, SW driven validation on Linux based… more
    L3Harris (10/12/25)
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  • Sr. DFT Design Engineer, AWS Machine…

    Amazon (Austin, TX)
    …a member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide ... possible today. Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test (DFT) architectures * Work with block designers to… more
    Amazon (09/25/25)
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  • Senior DFT Static Timing Analysis Engineer, Cloud

    Google (Sunnyvale, CA)
    …with an emphasis on computer architecture. + 10 years of experience in STA , and in leading test mode timing constraint development and timing convergence for ... SOC projects. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.… more
    Google (12/05/25)
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  • Sr Principal Product Engineer - Memory IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware , and IP that turn design ... and debug of Memory IP subsystems. + Support customer SOC and system integration, including ATE deployment and production...modern life depends on. We are a global electronic design automation company, providing software, hardware , and… more
    Cadence Design Systems, Inc. (11/22/25)
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  • Sr. Principal Solutions Engineer - Front End

    Cadence Design Systems, Inc. (Austin, TX)
    …the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware , and intellectual property to ... (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly… more
    Cadence Design Systems, Inc. (12/10/25)
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  • Senior Silicon Bringup and Test Lead, Raxium

    Google (Fremont, CA)
    …qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/ SoC ) design , with a focus on both digital logic ... practical experience. + 10 years of experience in analog circuit design , including simulation and verification. + Experience working with relevant Electronic… more
    Google (11/22/25)
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  • Lead Speed and Reliability Engineer - DFP

    NVIDIA (Santa Clara, CA)
    hardware engineering position. + Previous engineering experience in CPU/GPU/ SOC NPI bringup, with focus on driving methodologies and testplans. Familiarity ... a plus, related to timing, speed, reliability and power. + Familiarity with STA timing closure, circuit design , noise characterization, product binning methods… more
    NVIDIA (11/15/25)
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