- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- Micron Technology, Inc. (Dallas, TX)
- …the design and development of HBM base die SoC solutions, including top - level design , verification, and integration of various IP blocks. + Ensure ... signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate- level design... top talent to build a world-class HBM SoC design team. + Challenge the team… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... We are looking for SOC Design Engineer! The complexity of...complex GPU and Tegra chips and interface, directly with unit- level ASIC, Physical Design , CAD, Package … more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for an SOC Design Engineer opportunity? If yes,...sophisticated GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- Google (Sunnyvale, CA)
- …performance, efficiency, and integration. In this role, you will join a team working on SoC - level RTL design for our data center accelerators. You'll own ... instantiation, customization and generation of RTL. + Experience with SOC implementation standards and interfaces (eg AXI). + Experience...top - level RTL, architecture, design , and implementation of… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- Capgemini (San Francisco, CA)
- … convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, top level test plans, and verification. . 15 years' experience ... with SoC design (Digital design and development RTL) . Experience with chiplet architecture and partitioning for SiP packages. . Experience with various bus… more
- SpaceX (Irvine, CA)
- …STA Signoff. + Experience with power intent and upf development for block and soc top . + Familiar with formal verification and implementing functional ecos. + ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- The Boeing Company (Huntington Beach, CA)
- …industry standard Electronic Design Automation (EDA) tools and methodologies for digital ASIC/FPGA/ SoC design and verification - eg Synopsys VCS, Design ... Xilinx Vivado; and Universal Verification Methodology (UVM) + Experience working on large-scale SoC design teams. + Experience developing digital ASICs and SoCs… more
- Meta (Sunnyvale, CA)
- …the ML accelerator. 2. Define and track detailed internal integration test plans for top - level design components, and SOC vendor test plans and use case ... and/or C/C++ based verification. 11. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 12.… more
- The Boeing Company (Huntington Beach, CA)
- …(Virtuoso suite and Spectre simulator products) + Experience working on large-scale SoC design teams. + Experience developing Mixed-Signal circuits in ... is actively hiring an **Analog Mixed Signal Integrated Circuit Design Engineer (Associate, Mid- Level or Senior),** who...Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include… more
- Meta (Sunnyvale, CA)
- …3+ years of experience as a Digital Design Engineer. 9. Experience with top level integration using automation tools. 10. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 11. Experience in digital design … more
- Amazon (Boise, ID)
- …buses like AMBA AXI4 - Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains - Large breadth ... in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI,...with ARM and various DSP ISA - Experience debugging system- level issues - Experience in entire design … more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... Engineering or related technical field - 5+ years of experience in RTL design for SOC - 5+ years of experience VLSI engineering - 5+ years of experience… more
- Capgemini (San Francisco, CA)
- …latest Synopsys tools. The candidate should have a high aptitude for floor-planning the design of complex digital top level and/or blocks, with experience ... across the complete ASIC/ SOC design flow including routing, static timing closure, EM/IR analysis... floor planning, partitioning, timing budget generation, power planning, top - level PnR, CTS, block integration and ECO… more
- Cisco (San Jose, CA)
- …issues, provide solutions and ensure signoff clean results * Work with block and top level implementation teams to understand physical aspects and feedback on ... necessary updates * Work closely with block and TOP level physical implementation, IP development teams...with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical … more
- Micron Technology, Inc. (Minneapolis, MN)
- …test-benches. + Collaborating with other verification engineers to drive block, sub-system or SOC top level verification plans to closure. + Understanding ... inspiring the world to learn, communicate and advance faster than ever. As a Design Verification Engineer Intern for Micron, you will work with a highly innovative… more
- Axiom Space (Webster, TX)
- …+ Interface with external companies to create custom IP cores + Integrate IP cores into top - level FPGA design + Interface with software and PCB designers to ... ensure FPGA design meets system- level requirements + Generate ...design signals interfaces + Working knowledge of Xilinx design /debug tools and SoC (MPSoC or RFSoC)… more
- NVIDIA (Santa Clara, CA)
- …HSpice, Finesim, XA) + Experience in crafting test bench environments for component and top level circuit verification + Expertise in System Verilog or similar ... We are looking for an Engineer to verify the design and implementation of the world's leading SoC 's and GPU's. This position offers the opportunity to have real… more