• SoC Power Design Engineer

    Qualcomm (San Diego, CA)
    …of power intent design at SoC level + Generate and validate power intent design ( UPF ) at SoC level + Review designs and guide IP designers' power ... more
    Qualcomm (02/13/25)
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  • Principal Engineer - HBM SOC

    Micron Technology, Inc. (Richardson, TX)
    …that are transforming how the world uses information to enrich life. As an HBM SOC Design and Integration Engineer , you will be responsible for the ... more
    Micron Technology, Inc. (03/07/25)
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  • HBM SOC Design Engineer

    Micron Technology, Inc. (Dallas, TX)
    …technologies that are transforming how the world uses information to enrich life. As an HBM SOC Design Engineer , you will be responsible for the design ... more
    Micron Technology, Inc. (02/14/25)
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  • Sr. SOC /ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... more
    SpaceX (03/04/25)
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  • Sr. Physical Design Engineer

    Belcan (Palo Alto, CA)
    Sr. Physical Design Engineer Job Number: 354330 Category: ...contribute to all design phases of physical design of high performance SoC design ... more
    Belcan (01/15/25)
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  • ASIC Engineer , Physical Design

    Meta (Austin, TX)
    …execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs. 4. ... more
    Meta (01/25/25)
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  • ASICS Design Verification Engineer

    Qualcomm (Santa Clara, CA)
    …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from ... more
    Qualcomm (03/07/25)
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  • Digital Design Engineer

    Meta (Austin, TX)
    …SoCs that accelerate machine-learning and compute-vision workloads. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... more
    Meta (01/30/25)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (Santa Clara, CA)
    …** **Job Location: Santa Clara CA** **Job description:** We are seeking Digital Design (RTL) engineer for our full time role with Capgemini Engineering. ... more
    Capgemini (01/28/25)
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  • Silicon Digital Design Engineer

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... more
    Google (03/07/25)
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  • Senior Hardware Engineer

    Motion Recruitment Partners (Palo Alto, CA)
    Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer , you will ... more
    Motion Recruitment Partners (01/17/25)
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  • Lead CPU RTL Front End Design

    Google (Mountain View, CA)
    …or AI accelerators. + Experience with ARM Instruction Set Architecture. + Experience with SOC design , architect, and integration. Be part of a team that pushes ... more
    Google (02/22/25)
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  • Lead CPU RTL Design Engineer

    Google (Mountain View, CA)
    …or AI accelerators. + Experience with ARM Instruction Set Architecture. + Experience with SOC design , architect, and integration. Be part of a team that pushes ... more
    Google (02/15/25)
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  • Senior RTL Design Engineer , Camera,…

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... more
    Google (03/15/25)
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  • Machine Learning Performance Modeling…

    Meta (Sunnyvale, CA)
    **Summary:** We are currently seeking a machine learning performance modeling engineer to support the development of a custom machine learning software/hardware ... more
    Meta (01/09/25)
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  • Applications Engineer Consultant Functional…

    Siemens (Fremont, CA)
    …and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip ... more
    Siemens (03/04/25)
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  • Low Power ASIC Engineer (Next-Gen,…

    Qualcomm (San Diego, CA)
    …high performance ASIC/ SoC design flows (micro-architecture, RTL design , verification, synthesis, timing/STA, UPF , CLP, LEC formal verification, DFT, ... more
    Qualcomm (02/15/25)
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  • Senior Lead CPU RTL Engineer

    Google (Portland, OR)
    …or AI accelerators. + Experience with ARM Instruction Set Architecture. + Experience with SOC design , architect, and integration. Be part of a team that pushes ... more
    Google (03/13/25)
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