- Qualcomm (San Diego, CA)
- …of power intent design at SoC level + Generate and validate power intent design ( UPF ) at SoC level + Review designs and guide IP designers' power ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...primary role is to implement and validate low power design intent requirements at the SoC -level. The… more
- Micron Technology, Inc. (Richardson, TX)
- …that are transforming how the world uses information to enrich life. As an HBM SOC Design and Integration Engineer , you will be responsible for the ... is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design , IP Integration,...performance and low power consumption and how to use UPF . + Good knowledge of static timing analysis, synthesis… more
- Micron Technology, Inc. (Dallas, TX)
- …technologies that are transforming how the world uses information to enrich life. As an HBM SOC Design Engineer , you will be responsible for the design ... is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design , IP Integration,...performance and low power consumption and how to use UPF . + Good knowledge of static timing analysis, synthesis… more
- SpaceX (Irvine, CA)
- Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...and STA Signoff. + Experience with power intent and upf development for block and soc top.… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: ...contribute to all design phases of physical design of high performance SoC design ... Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 /hr. Location:...to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity… more
- Meta (Austin, TX)
- …execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs. 4. ... Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design … more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from ... development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to… more
- Meta (Austin, TX)
- …SoCs that accelerate machine-learning and compute-vision workloads. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... Qualifications: 8. 3+ years of experience as a Hardware Design Engineer for production silicon shipped in...design uArchitecture and RTL coding 10. Experience in SoC bus and interconnect protocols 11. Experience with at… more
- Capgemini (Santa Clara, CA)
- …** **Job Location: Santa Clara CA** **Job description:** We are seeking Digital Design (RTL) engineer for our full time role with Capgemini Engineering. ... using Verilog/System Verilog/VHDL. + Develop and implement low power design ( UPF /CPF). + Design top...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Digital Design (RTL) Engineer_ **Location:**… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... to optimize RTL code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD in Electrical Engineering,… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer , you will ... contribute to all design phases of physical design of high performance SoC design...to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity… more
- Google (Mountain View, CA)
- …or AI accelerators. + Experience with ARM Instruction Set Architecture. + Experience with SOC design , architect, and integration. Be part of a team that pushes ... + Experience with RTL language (System Verilog) and related design processes (eg, Lint, UPF ). Preferred qualifications: + Master's degree or PhD in Electrical… more
- Google (Mountain View, CA)
- …or AI accelerators. + Experience with ARM Instruction Set Architecture. + Experience with SOC design , architect, and integration. Be part of a team that pushes ... + Experience with RTL language (System Verilog) and related design processes (eg, Lint, UPF ). Preferred qualifications: + Master's degree or PhD in Electrical… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... techniques to optimize RTL code, performance and power as well as low-power design techniques. + Experience with a scripting language such as Perl or Python.… more
- Meta (Sunnyvale, CA)
- **Summary:** We are currently seeking a machine learning performance modeling engineer to support the development of a custom machine learning software/hardware ... SoCs for AR/VR devices. **Required Skills:** Machine Learning Performance Modeling Engineer Responsibilities: 1. Lead power and performance modeling of IP components… more
- Siemens (Fremont, CA)
- …and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip ... design . We have a unique company culture. With its...competent leadership from our managers and executives. This Applications Engineer (AE) position delivers technical expertise for Functional Verification… more
- Qualcomm (San Diego, CA)
- …high performance ASIC/ SoC design flows (micro-architecture, RTL design , verification, synthesis, timing/STA, UPF , CLP, LEC formal verification, DFT, ... and, ability to execute critical power analysis of critical design IPs for path to DDR. This is a...This is a great opportunity to join a fast-paced SoC team responsible for development of next Generation, high… more
- Cadence Design Systems, Inc. (Moylan, MN)
- …C / C++ / System-C / TLM / Specman e + Familiar with the full SoC design flow + Excellent problem-solving skills and good presentation and communication skills ... an impact on the world of technology. We are looking for an Application Engineer System Verification, based in Grenoble or Paris-Velizy Job purpose : The successful… more
- Google (Portland, OR)
- …or AI accelerators. + Experience with ARM Instruction Set Architecture. + Experience with SOC design , architect, and integration. Be part of a team that pushes ... Verilog or SystemVerilog. + Experience with RTL language (eg SystemVerilog) and related design processes (eg, Lint, UPF ). Preferred qualifications: + PhD in… more