- Mission Support and Test Services (Mercury, NV)
- …security challenges facing the world today. + MSTS offers our full -time employees highly competitive salaries and benefits packages including medical, dental, ... Jacobs Engineering Group Inc. (Jacobs), and HII Nuclear Inc. **Responsiblities** The Senior Civil Engineer will support the roads, construction and water systems in… more
- Battelle Memorial Institute (Columbus, OH)
- …this role involves close collaboration with a diversity of staff operating in physical laboratories and production environments, the role is onsite at our Columbus ... on program execution and delivery issues. + Represents Battelle to senior leadership in client organizations. Prepares and presents presentations to internal… more
- Micron Technology, Inc. (San Jose, CA)
- …performance and reliability of non-volatile memory products. **Position Overview** The Senior Member of Technical Staff Design Engineer in Micron's NVEG organization ... and optimization of datapath circuits for NAND flash memory. This senior -level position will support design feasibility studies, evaluate impacts, and explore… more
- SpaceX (Sunnyvale, CA)
- Sr . Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . FULL CHIP PHYSICAL...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year… more
- Amazon (Cupertino, CA)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and… more
- SpaceX (Bastrop, TX)
- Sr . IC Packaging Test Engineer, Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. SR . IC PACKAGING TEST ENGINEER, SILICON TECHNOLOGY (STARLINK) SpaceX...will work closely with test equipment manufacturers and in-house chip & system designers to develop and release production… more
- Amazon (Austin, TX)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies...of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For… more
- Teledyne (Camarillo, CA)
- …integrity, metal density rules, transistor, and capacitor matching. + Strong background with full custom circuit, block, and chip layout using Cadence Virtuoso ... the next level with us** ! Teledyne Imaging Sensors is looking for a ** Sr . Manager, Mixed Signal IC Design** responsible for supporting the Read Out Integrated… more
- Global Foundries (Malta, NY)
- About GlobalFoundries: GlobalFoundries is a leading full -service semiconductor foundry providing a unique combination of design, development, and fabrication ... strong focus on assembly process interactions for each step in a SiPh Flip Chip package towards delivery of product solutions . Focus on product and module… more
- Global Foundries (UT)
- About GlobalFoundries: GlobalFoundries is a leading full -service semiconductor foundry providing a unique combination of design, development, and fabrication ... and driving customer satisfaction. + Develop and implement strategic sales plans to grow chip and wafer sales within the aerospace and defense sectors. + Own the… more
- Amazon (Austin, TX)
- …- MS degree in EE, CE or CS - Good breadth of knowledge in chip design from micro-architecture through physical design - Good knowledge of design verification ... block designers to integrate DFT implementations * Work with physical design team to setup and implement DFT insertion...of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For… more
- Intel Corporation (Hillsboro, OR)
- …automation. + Builds deep understanding of digital design, verification, structural and physical layout, full - chip integration, power, and performance ... memory compilers (eg, bitcells, SRAMs, Register Files). + Performs detailed physical array planning, area optimization, digital block synthesis, critical wire… more
- Northrop Grumman (Jessup, MD)
- …are seeking a front-end ASIC design engineer for design and verification of full -custom digital circuits. Must be proficient in Verilog, System Verilog or VHDL RTL ... constraints and timing closure. Automated place and route and physical verification knowledge is a plus. Must have strong...can be filled at the Principal level OR the Sr . Principal level. Qualifications for both are listed below:**… more
- NVIDIA (Santa Clara, CA)
- …of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as ... and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to...+ Background with logic synthesis at either block or full - chip level, at project execution and/or flow… more
- Northrop Grumman (Jessup, MD)
- …be a part of our mission! Northrop Grumman Mission Systems (NGMS) is seeking a Sr . Staff ASIC Physical Design Engineer to support our growing engineering team in ... MD. **Roles and Responsibilities:** + Responsible for the complete physical implementation at both block and chip ...obtain/maintain an Active DoD secret clearance + Experience in full product life cycle of ASIC Design + Proficient… more
- NVIDIA (Santa Clara, CA)
- …of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including ... with 2+ years experience in Synthesis and Timing + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA), timing constraints generation and… more
- Google (Sunnyvale, CA)
- …equivalent practical experience. + 5 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification, full ... Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_...Knowledge of semiconductor device physics and SPICE simulation and full - chip static timing topics. **About the job**… more
- Cisco (San Jose, CA)
- …ASIC experience. + Experience with microarchitecture and RTL implementation. + Experience with block/ full chip SDC development in functional and test modes. + ... ** Sr . ASIC Engineer** The application window is expected...will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and… more
- NVIDIA (Westford, MA)
- …of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. + Analyze and optimize design constraints and synthesis ... Timing tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in full - chip /sub- chip Static Timing Analysis (STA), timing constraints generation… more
- Cisco (Carlsbad, CA)
- …if a sufficient number of applications are received. **Meet the Team** The Senior Director of Silicon Engineering leads the Cisco's Silicon Engineering Team within ... team is following best engineering practices in the development, physical design, layout, simulation, validation/characterization, & documentation of the silicon… more
