- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL ...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year… more
- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING SIGNOFF &...ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) + Analysis of clock domain crossing paths… more
- Amazon (San Diego, CA)
- …looking for a Sr . Technical Program Manager with experience in ASIC / SOC development, from architecture to pre-production stages, project management, and ... Key job responsibilities In this role you will: - Collaborate with engineering leaders ( ASIC / SOC leads) to create project execution plans for ASIC / SOC… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- Amazon (San Diego, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Sr . SOC Design Engineer-STA to continue to innovate on behalf of our customers. ... - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. - Full chip timing constraints development, full chip / Sub-System STA and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... leading SoC 's and GPU's. This position offers you a unique...opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... top level and/or blocks, with experience across the complete ASIC / SOC design flow including routing, static timing...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The Clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of ... SOC clocking. The team collaborates with the front end...floor-planning and back end teams to help craft the physical floorplan of the chip and explains the programming… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically...and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis,… more
- Cisco (San Jose, CA)
- …hardware solutions. What You'll Do * Be part of the development organization as an Senior ASIC Design Engineer with primary focus on RTL Design. * Create ... bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route...work with SDK and Software teams as part of ASIC development to create a seamless handshake between hardware… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU ... floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the...team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency… more
- Amazon (Sunnyvale, CA)
- …complete the execution of projects in time. Key job responsibilities As a Senior SoC Technical Program Manager, you will interface with cross-functional ... you will interface with cross-functional engineering and program/product management teams to develop ASIC / SOC solutions that will go into Amazon Devices. In this… more
- NVIDIA (Santa Clara, CA)
- …Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design, VLSI and platform teams. Our SoC architects excel at ... We are looking for a Senior Hardware SoC Architect for our...This involves working with other IP architects, designers, verification, Physical Design, Software, DFT, Security, Automotive Safety and others.… more
- NVIDIA (Santa Clara, CA)
- …computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip ( SOC ) group is looking for a top ASIC Engineer with a curiosity ... Are you looking for an SOC Design Engineer opportunity? If yes, come and...GPU and Tegra chips and interact directly with unit-level ASIC , Physical Design, CAD, Package Design, Software,… more
- Qualcomm (San Diego, CA)
- …without losing track, and foresee and plan around obstacles. + Proficient in running Physical synthesis with Synopsys Fusion Compiler on SoC Top Level blocks ... to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate,… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr . DDR IP Design Engineer (Silicon Engineering) at...cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
- Capgemini (San Francisco, CA)
- …Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC / SOC project design and development + Hands on with Cadence tools, DFT flow ... & physical aware flow + Prior experience of synthesizing high...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
- The Boeing Company (Huntington Beach, CA)
- …industry standard Electronic Design Automation (EDA) tools and methodologies for digital ASIC /FPGA/ SoC design and verification - eg Synopsys VCS, Design ... external wafer fabrication but performs design (architecture, RTL, synthesis, circuits, physical design, verification, packaging and test) in house. SSED has… more
- Capgemini (San Jose, CA)
- …programming and experience with SimPy. + Experience with Synopsys or Cadence EDA tools and ASIC / SOC Power Analysis Tools. + Deep understanding of SoC design ... **Job Role: Senior ** **Performance Modeling Engineer** **Job Location: San Jose...ideal candidate will have a deep understanding of System-on-Chip ( SoC ) design and architecture, as well as Expertise in… more
- Microsoft Corporation (Santa Clara, CA)
- …key components of functional validation of complex Application-Specific Integrated Circuit ( ASIC ) System on Chip ( SOC ) using Universal Verification Methodology ... Azure Hardware Systems & Infrastructure group is seeking a ** Senior Silicon Engineer** . You will join our front-end...(UVM)/C test bench + Perform Pre-Silicon SoC verification, Post-Silicon/ Field-Programmable Gate Array (FPGA) validation by… more
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