- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual level and… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) at... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- Amazon (Austin, TX)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- Qualcomm (San Diego, CA)
- …entering new area such as the PC market. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides ASIC and/or FPGA ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and methodology...As new projects are coming up, making it wonderful timing to join our team. An ideal candidate will… more
- Amazon (Redmond, WA)
- …role you will: . Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. . Define, ... configure and integration SoC Subsystems . Contribute to the SoC ...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... leading SoC 's and GPU's. This position offers you a unique...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... fully verified design by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing . Analyze simulation results, identify and ... Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- Cisco (San Jose, CA)
- …in the world. You will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software ... working together to ensure the successful deployment of the ASIC in products. Your Impact Key responsibilities: * Development...complex RTL designs. * Implement Verilog RTL to meet timing and performance requirements. * Analyze code coverage and… more
- Amazon (Austin, TX)
- …Bandwidth Memory (HBM) DRAM interface and memory stack testing, including training of the SOC phy to DRAM base die, stretching beyond JEDEC specs to gain maximum ... how to glean quality of connection from eye diagrams, timing margin etc. You will also work with the...building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind,… more
- Qualcomm (Santa Clara, CA)
- …volume chip production for at least one product cycle is preferred **Keywords** : ASIC ; SOC ; Low Power; Power estimates; Power Intent; Power Implementation; WiFi ... Technology team you will be working on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates and power… more
- Qualcomm (Austin, TX)
- …as the PC and the Data Center markets. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and methodology...new projects are coming up, it is a wonderful timing to join our team and take part in… more
- L3Harris (Camden, NJ)
- …land, sea and cyber domains in the interest of national security. Job Title: Sr ASIC /FPGA VHDL Design Engineer Job Code: 21408 Job Location: Camden, ... Friday off Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff...+ Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA) + Perform RTL quality using: Lint,… more
- The Boeing Company (Huntington Beach, CA)
- …industry standard Electronic Design Automation (EDA) tools and methodologies for digital ASIC /FPGA/ SoC design and verification - eg Synopsys VCS, Design ... We are seeking a **Digital Integrated Circuit Design Engineer (Mid-Level, Senior or Lead)** with experience developing complex, high-performance ASICs, FPGAs, and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Hardware Design Engineer for our Tegra group! NVIDIA is seeking passionate Senior Hardware Design Engineers to architect, design ... and verify the world's leading SoC 's and GPU's. This position offers the opportunity to...architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. What… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... as one of the key IPs in many complex SoC . You'll work closely with analog designers and system...define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to...and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis,… more