- Capgemini (Sunnyvale, CA)
- …seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug ... should be available to work during the US work hours. **Key responsibilities:** + System verilog real number modeling + Writing regression tests for analog… more
- Textron (Wilmington, MA)
- …be to support the verification of FPGA and ASIC designs for our electronic systems \. The FPGA/ASIC Design Verification Engineer will be required to work ... Systems is looking for a FPGA/ASIC Design Verification \(DV\) Engineer whose primary job function...* Develop test benches for FPGA or ASIC design verification using UVM, System Verilog ,… more
- Texas Instruments (Dallas, TX)
- …Electrical Engineering or related field + 5 years of Analog Mixed Signal verification experience utilizing System Verilog **Preferred qualifications:** + ... part in shaping it.** Texas Instruments is seeking Design Verification Engineer . In this role you will...analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require… more
- Capgemini (Santa Clara, CA)
- …of experience in pre-silicon design verification * Proficiency in C-shell scripting, Verilog -HDL & System Verilog . * Strong knowledge in SV Assertions, ... **Job Title:** **Design Verification Engineer ** **Job Location: Santa Clara...Location: Santa Clara CA** **Job description:** *Architect and Create verification environments using System - Verilog and… more
- The Boeing Company (Kent, WA)
- …stakeholders + Experience with hardware emulators, especially Palladium + Proficiency with hardware verification languages: System Verilog , System ... of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems ). As an ASIC/FPGA Engineer on the Boeing Electronic Products… more
- Randstad US (Mountain View, CA)
- …Friendly, supportive, and collaborative. Candidate Requirements + Experience: + 7+ years in UVM/ System Verilog verification . + 7+ years of scripting ... silicon verification engineer . + mountain view ,...Mountain View, CA area. This role focuses on pre-silicon verification using UVM/ System Verilog , involving… more
- Qualcomm (San Diego, CA)
- …tools. + Creates and maintains verification test benches and environments in System Verilog /UVM + Create and leverage advanced testing frameworks to generate ... + Verification skills: Test planning, Scripting, Simulation, problem solving and debug. + System Verilog , UVM, Verilog or VHDL, C/C++ skills required. +… more
- Broadcom (Mendota Heights, MN)
- …Set Required** + Good understanding of Verilog and system Verilog + Good understanding of Universal Verification Methodology (UVM) + Understanding of ... Account, please Sign-In before you apply.** **Job Description:** **Design Verification and DFT Engineer ** We are looking... system Verilog assertions + Familiar with memory behavior + Good… more
- Skyworks (Hillsboro, OR)
- …with system -level verification in ASICs + Experience in implementation with Verilog and System Verilog + Experience in post-processing with Python + ... Digital Verification Engineer Apply now " Date:Oct...to simulation-based testing, your ability to use FPGAs in system -level verification , as well as your ability… more
- RTX Corporation (Marlborough, MA)
- …in Universal Verification Methodology Framework (UVMF) * Experience in both System - Verilog and VHDL languages * Successfully have completed several designs ... world safe from foreign threats. As a Principal Firmware Verification Engineer , you will be a member... architecture, test plans, and coverage * Build UVMF/ System - Verilog based test benches with agents, predictors,… more
- Broadcom (San Jose, CA)
- …Skills/Expertise: + Expertise in formal verification . + Strong understanding of System Verilog assertions and ability to quickly write effective coverage and ... assertion properties. Ability to understand Verilog designs and develop relevant verification properties....support for design IPs or VIPs. + Expertise in System Verilog especially writing SVAs for formal.… more
- Meta (Redmond, WA)
- …9. 10+ years of AMS design verification experience. 10. Fluent in System Verilog and real number modeling. 11. Experience with UVM verification ... products. We are seeking an Analog and Mixed Signal Verification engineer to lead analog mixed signal...AMS test benches to verify pre-silicon designs. 3. Build System Verilog real number analog behavioral models,… more
- Capgemini (San Francisco, CA)
- …: San Francisco CA / Sunnyvale CA** **Job description:** Architect and Create verification environments using System - Verilog and UVM (Universal ... + Proficiency and proven work experience in UVM & System Verilog based DV development. + Strong...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Lead DV IP Verification Engineer_… more
- NVIDIA (Santa Clara, CA)
- …to implement abstraction techniques for effective verification . + Hands-on experience with Verilog / System Verilog HDLs, temporal logic assertions, and ... NVIDIA is looking for Formal Verification Engineer to help verify the design and implementation of industry's leading CPUs and other High Performance Computing… more
- NVIDIA (Santa Clara, CA)
- We're now looking for an ASIC Verification Engineer - New College Grad!... level verification + Strong background in Verilog / System Verilog / ... NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of...doing: + As a key member of our ASIC Verification team, you will verify the design and implementation… more
- Cisco (San Jose, CA)
- …years of related ASIC design verification experience. * Proficient in ASIC verification using UVM/ System Verilog . * Proficient in verifying complex ... Unit is on the lookout for a driven Senior Verification Engineer to join us in developing...building test benches from scratch, hands on experience with System Verilog constraints, structures and classes. *… more
- NVIDIA (Santa Clara, CA)
- …tools and state of the art verification methodologies. This includes coding in System Verilog , UVM, C++, Perl, Python and NVIDIA custom compilers and tools. ... Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design...-level verification . + Strong coding skills in System Verilog , scripting languages (Perl/python) and C++.… more
- NVIDIA (Santa Clara, CA)
- …or system level verification . + Proficiency with Object Oriented Programming, System Verilog , Verilog , UVM. + Strong skills with VCS or equivalent ... NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off...Clocking and Silicon Correlation + Own the unit and system level verification of various IPs, create… more
- Qualcomm (Santa Clara, CA)
- …, and general computational logic design/ verification concepts + Experience in Verilog / System Verilog and UVM/OVM + Strong debugging, Analytical and ... with Design teams + Expertise in IP level / Sub- system level verification + Understanding of standard...+ Experience in developing Monitors, Scoreboards, Sequencers that utilize System Verilog , UVM, and/or other methodologies +… more
- NVIDIA (Santa Clara, CA)
- …degrees (MS, PhD) + 5+ years of relevant work experience + Proficiency in verification languages ( System Verilog or equivalent) and methodologies (UVM or ... We are now looking for a Senior ASIC Verification Engineer ! NVIDIA is seeking an...other high-speed IO protocol experience is desirable + Strong System Verilog or UVM experience The base… more
Related Job Searches:
Engineer,
System,
System Engineer,
System Verilog,
Verification,
Verification Engineer,
Verilog