- IBM (Houston, TX)
- …design, code development, verification, integration and performance targets * Design System Verilog code and integrate IP into the larger design * Work with ... Technical and Professional Expertise * 5+ years of Experience with Verilog and/or System Verilog development * UVM experience * Bachelor's degree in Computer… more
- Qualcomm (Boxborough, MA)
- …years of academic experience with programming languages such as C, C++, Python, Perl, Verilog , SystemVerilog etc. + Must be available for 11 - 14 weeks during Summer ... + Graphics power analysis & optimization (Vulkan) + C, Perl, Verilog , System Verilog , C++, Python **_CPU_** + Validation of concepts and high-level system… more
- Skyworks (Austin, TX)
- …production. Responsibilities + + Digital design specification, design, analysis, and HDL ( Verilog /System Verilog ) coding + Behavioral modeling of analog and ... Minimum Requirements + + Digital design specification, design, analysis, and HDL ( Verilog /System Verilog ) coding + Behavioral modeling of analog and mixed… more
- Lockheed Martin (Orlando, FL)
- …Global DEI\. **Basic Qualifications:** \- HDL programming experience with VHDL, Verilog , and/or System Verilog \- Experience in Hardware\-Software Integration ... \- Familiarity with FPGA toolsets \(Vivado/Vitis\) **Desired Skills:** \- Experience with System\- Verilog , Verilog , C/C\+\+, MatLab / Simulink, System Verilog… more
- Textron (Wilmington, MA)
- …Develop test benches for FPGA or ASIC design verification using UVM, System Verilog , Verilog or VHDL * Conduct various verification activities including creating ... and/or ASIC verification design * Experience in UVM, System Verilog , C and scripting languages * Experience with ...Verilog , C and scripting languages * Experience with Verilog simulation tools such as QuestaSim, VCS or Xcelium… more
- Actalent (Morrisville, NC)
- …3 Hard Skills Required + Additional 1. Minimum 7 years experience with UVM/System Verilog 2. Minimum 7 years experience with scripting language 3. Minimum 7 years ... and debug tests in UVM * Must be able to implement a UVM/System verilog test bench from scratch, create agents, scoreboards, checks, assertions, cover-points. * Must… more
- Western Digital (Roseville, CA)
- …candidate will have a strong background in both logic design, with extensive Verilog coding experience, and a good understanding of physical design. This role ... RESPONSIBILITIES + Design and implement complex ASICs using System Verilog + Technical oversee of physical design process, including...and good understanding of physical design + Proficient in Verilog and System Verilog for RTL design… more
- Microsoft Corporation (Raleigh, NC)
- …of a DRAM Memory Controller and implement the design with high quality in Verilog Register Transfer Level (RTL). + Interface with PHY vendor. + Work closely with ... design. + Implement any additional required functional units in Verilog . + Ensure high quality of the design from...Device Engineering Council (JEDEC) DDR5 Specification. + Fluency in Verilog and System Verilog and Dynamic Random-Access… more
- Meta (Austin, TX)
- …Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. RTL development using Verilog , System Verilog and HLS 4. Lint, CDC, Synthesis, ... record of first-pass success in ASIC Development 10. Experience with Verilog or System Verilog 11. Experience in one of these skills: Micro-architecture and RTL… more
- Broadcom (Mendota Heights, MN)
- …Responsibilities** + Work with design engineers to create test plans + Implement Verilog testbenches + Debug simulation errors and issues + Work with design ... DFT deliverables **Skill Set Required** + Good understanding of Verilog and system Verilog + Good understanding of Universal Verification Methodology (UVM) +… more
- Texas Instruments (Dallas, TX)
- …+ 5 years of Analog Mixed Signal verification experience utilizing System Verilog **Preferred qualifications:** + Experience using Verilog , SystemVerilog, ... Verilog -A, Verilog -AMS, Python, UVM, Cadence ADE-L/ADE-XL or Maestro + Strong background with EDA design tools and UNIX design environment + Understanding of analog circuits and systems, particularly power systems + Ability to write analog models in one… more
- Cisco (San Jose, CA)
- …Design. * Create micro-architecture specifications and participate in reviews * Implement Verilog RTL to meet timing and performance requirements. * Help define, ... with developing Micro-Architecture for blocks * Prior experience with Verilog /System Verilog * Prior experience with Clock Domain, Reset Domain Crossing… more
- University of Southern California (Arlington, VA)
- …Science required. + Strong software development (C++/Java/Python) and hardware design (VHDL/ Verilog /System Verilog ) experience. + 3-5 years of experience using ... Science required. Strong software development (C++/Java/Python) and hardware design (VHDL/ Verilog /System Verilog ) experience. 3-5 years of experience using… more
- Meta (Sunnyvale, CA)
- …ASIC Engineer, Design Responsibilities: 1. Micro-architecture development. 2. RTL development using Verilog , System Verilog and HLS. 3. Lint, CDC, Synthesis, & ... 7. 3+ years of silicon development experience. 8. Experience with Verilog or System Verilog . 9. Experience in one of these skills (minimum 3 years):… more
- Capgemini (Sunnyvale, CA)
- …are seeking Mixed signal Design Verification Engineer who is proficient in system verilog real number modeling and experience with UVM. Proficient in debug skills ... available to work during the US work hours. **Key responsibilities:** + System verilog real number modeling + Writing regression tests for analog behavioral model… more
- Northrop Grumman (Mcclellan, CA)
- …mixed signal superconducting processor circuits. Must be proficient in HDL (VHDL/ Verilog ) and HVL (SystemVerilog). Experience with SystemVerilog Assertions (SVA) and ... years with technical MS; 0 years with PhD) - Experience in HDL (VHDL/ Verilog ) and HVL (SystemVerilog) + Experience with SystemVerilog Assertions (SVA) + Knowledge of… more
- Randstad US (Mountain View, CA)
- …View, CA area. This role focuses on pre-silicon verification using UVM/System Verilog , involving test writing, debugging, and scripting in a collaborative team ... Candidate Requirements + Experience: + 7+ years in UVM/System Verilog verification. + 7+ years of scripting experience (eg,...of end-to-end testing involvement. Top Hard Skills: + UVM/System Verilog (7+ years). + Scripting (7+ years). + Test… more
- The Boeing Company (Kent, WA)
- …detailed design implementation and functional verification using SystemVerilog/VHDL/ Verilog **Preferred Qualifications (Desired Skills/Experience)** + Proven record ... emulators, especially Palladium + Proficiency with hardware verification languages: System Verilog , System Verilog Assertions + Proficiency with Object Oriented… more
- Cisco (San Jose, CA)
- …Design * Create micro-architecture specifications and participate in reviews * Implement Verilog RTL to meet timing and performance requirements * Help define, ... CE and 0 years of related experience * Prior experience with Verilog /System Verilog programming skills * Prior experience with simulators/synthesis/static timing… more
- Amazon (Cupertino, CA)
- …2025 and September 2026 - Programming experience in C/C+- Programming experience in System Verilog or Verilog Preferred Qualifications - Enrolled in MS degree or ... higher in EE or CE - Experience testing Verilog designs - Experience implementing computer architecture concepts - Proficiency with a scripting language (Python or… more
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