• Physical Design Engineer

    Google (Sunnyvale, CA)
    …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Physical Design Engineer on the chip implementation team, ... equivalent practical experience. + 8 years of experience in static timing (ie, full chip timing signoff ownership, constraint...analysis. + Experience leading one or more aspects of physical design or physical more
    Google (09/24/24)
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  • Physical Design Engineer

    SpaceX (Sunnyvale, CA)
    Physical Design Engineer (Silicon...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical ... possible, with the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
    SpaceX (10/01/24)
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  • Senior Physical Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
    NVIDIA (10/03/24)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... amplify human inventiveness and intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block… more
    NVIDIA (09/25/24)
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  • Senior Silicon Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …cloud servers, clients, and augmented reality. We are looking for a **Senior** **Silicon** ** Design Engineer ** to work on leading edge custom IP development as ... logic design in SystemVerilog/Verilog/VHDL + 3+ years experience running synthesis/ static check tools including RTL synthesis, lint, CDC, RDC, and/or LEC.… more
    Microsoft Corporation (10/03/24)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... analysis on the design . + Drive the design and physical implementation of digital and/or...Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for… more
    NVIDIA (08/31/24)
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  • Senior C++ Software Engineer - Chip…

    NVIDIA (Santa Clara, CA)
    …algorithms, computer architecture and computer science theory + Experienced with VLSI physical design and packaging + Passionate about SW development processes ... design technologies such as CoWoS-L. As a software engineer , you will craft highly efficient software to automate...C++, compiler, build systems, and database. + Experienced with static and dynamic code analysis tools The base salary… more
    NVIDIA (09/04/24)
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  • Senior C++ Software Engineer - Chip…

    NVIDIA (Santa Clara, CA)
    …algorithms, computer architecture and computer science theory + Experienced with VLSI physical design and packaging + Flexibility/adaptability for working in a ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level… more
    NVIDIA (07/14/24)
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  • Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …block and Chip top level You will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R, and participating in silicon ... RTL design of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts. Knowledge of the… more
    Cadence Design Systems, Inc. (08/01/24)
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  • SerDes RTL Senior Principal Digital Design

    Cadence Design Systems, Inc. (San Jose, CA)
    static timing analysis and constraint development + Understanding of fundamental physical design flows and stages + Understanding impacts of analog and ... to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly… more
    Cadence Design Systems, Inc. (07/06/24)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …circuits for hardware security, adaptive clocking and power management solutions + Drive the design and physical implementation of custom digital IPs from RTL to ... impact on the world! What you'll be doing: + Participate in ground breaking Processor design in deep submicron technologies. + Work as part of a global circuits team… more
    NVIDIA (08/14/24)
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  • Lead Finite Element Analysis Engineer

    Snap Inc. (Palo Alto, CA)
    …pair of glasses that bring augmented reality to life. We're looking for a Staff FEA engineer to join the Snap Lab team at Snap Inc! What you'll do: + Provide ... for Snap Lab's structural engineering analysis efforts. + Perform static and dynamic structural simulations using Abaqus _(preferred)_ or...who may assist in simulation tasks or testing of physical parts. + Lead and coordinate with partner teams… more
    Snap Inc. (08/27/24)
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  • Senior Plan Reviewer/ Engineer ; Plan Check…

    City of Palo Alto (Palo Alto, CA)
    …+ Knowledge of fundamentals of structural design involving principles of static and dynamics. + Ability to maintain physical condition appropriate to ... (2) years of progressively responsible experience as a project engineer in the structural design of commercial,...as a project engineer in the structural design of commercial, industrial, and multifamily residential buildings. This… more
    City of Palo Alto (08/28/24)
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  • Sr. Principal STA Solutions Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …Computer Engineering. + Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction. + Good understanding of Cadence ... Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should… more
    Cadence Design Systems, Inc. (10/01/24)
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  • Security Engineer III (Network Security)

    Ross Stores, Inc. (Dublin, CA)
    …procedures and protocols to ensure integrity and compliance\. The Network Security Engineer leads the product area strategy, roadmap, design , and vendor/product ... and development for our teams\. **GENERAL PURPOSE:** The Network Security Engineer III is responsible for thinking strategically, envisioning, and taking steps… more
    Ross Stores, Inc. (09/12/24)
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  • Lead Software Engineer , Synthesis

    Cadence Design Systems, Inc. (San Jose, CA)
    …Solution product. Genus is a complete product that encompasses logic synthesis and physical design . The product breadth means we are looking for skilled ... to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on… more
    Cadence Design Systems, Inc. (07/11/24)
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  • Senior C++ Software Engineer

    NVIDIA (Santa Clara, CA)
    …and requirements. Ways to stand out from the crowd: + Experienced with VLSI physical design and packaging. + Good hardware architecture and RTL design ... team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, RTL, and gate level… more
    NVIDIA (08/24/24)
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  • Principal Product Security Engineer

    Palo Alto Networks (Santa Clara, CA)
    …we all win with precision. **Your Career** As the Principal Product Security Engineer on the Infosec Product Security team, you will be responsible for building ... coverage and time to action + Participate in the design and implementation of secure software development processes, including...tools benchmarking and fine tuning + Perform code reviews, static code analysis, and security testing to identify and… more
    Palo Alto Networks (08/25/24)
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  • Formal Verification Product focused Application…

    Siemens Digital Industries Software (Fremont, CA)
    …ID:** 435981 Siemens EDA Business is a global technology leader in electronic design automation software. Our software tools enable companies around the globe to ... the increasingly complex world of chip, board, and system design . **Position Overview:** The Product focused AE for Formal...of formal tools + Hand-on experience with QOSF (Questa-OneSpin Static and Formal) platform products is desired, but not… more
    Siemens Digital Industries Software (09/18/24)
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  • Research Scientist Intern, 3D Machine Perception…

    Meta (Sunnyvale, CA)
    …Research novel object/scene reconstruction method to recover the physical properties or functionality of real-world objects/environments with egocentric ... machine perception. Build up the related dataset for physical scene understanding.- Egocentric human states estimation and motion understanding with multimodal… more
    Meta (09/18/24)
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