- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for a SOC Design Engineer opportunity? If yes,...complex GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- SpaceX (Sunnyvale, CA)
- …STA Signoff. + Experience with power intent and upf development for block and soc top . + Familiar with formal verification and implementing functional ecos. + ... Sr. SOC /ASIC Synthesis & Front-End STA Engineer (Silicon Engineering)... and timing closure + Deep understanding of ASIC design flow, top -down and bottom-up design… more
- Meta (Sunnyvale, CA)
- …7+ years of experience as a Digital Design Engineer 10. Experience with top level integration using automation tools. 11. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 12. Experience in digital design … more
- Amazon (Sunnyvale, CA)
- …buses like AMBA AXI4 - Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains - Large breadth ... in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI,...with ARM and various DSP ISA - Experience debugging system- level issues - Experience in entire design … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …timing closure, power optimization, and physical verification for both of block and Chip top level You will also be responsible for interfacing with the Physical ... of technology. As a core member of the PHY Design team, your responsibilities will span across various aspects...teams in multiple successful ASIC/IP tapeouts. Knowledge of the IP/ SoC level timing closure flow and methodology.… more
- NVIDIA (Santa Clara, CA)
- …HSpice, Finesim, XA) + Experience in crafting test bench environments for component and top level circuit verification + Expertise in System Verilog or similar ... We are looking for an Engineer to verify the design and implementation of the world's leading SoC 's and GPU's. This position offers the opportunity to have real… more
- Meta (Sunnyvale, CA)
- …verification and UVM methodology. 10. 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... and track detailed test plans for the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test… more
- ManpowerGroup (Mountain View, CA)
- …devices including server, mobile, and custom hardware. **Key Responsibilities:** + Conduct SoC or System- level power analysis to optimize performance and ... **Job Title:** Hardware Design Engineer 5 **Location:** Mountain View, CA (5...6 - 18 Months **Pay Range:** $80/hr. - $85/hr. ** Top 3 Required Skills and Experience:** 1. **Silicon Power… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Palladium and Protium Emulation products to enable the critical shift-left of System Level SOC verification and Validation for Cadence customers. This position ... that combine a Virtual Machine running a production OS with the customer's SOC Design running on Candence's Palladium emulation or Protium Prototyping platforms.… more
- Amazon (Sunnyvale, CA)
- …Engineering. - 7+ years in semiconductor companies as a Sr. DFT Engineer. - Top level DFT architecture definition experience. - Scan insertion tools and ... in writing verilog/system verilog RTL related to DFT logic design . - Experience in Chip level DFT...level DFT verification methodology and flow. - Perform SOC /IP DFT Gate- level simulations. - Static timing… more
- Meta (Sunnyvale, CA)
- …generic compute units to custom silicon IP blocks, traditional compute benchmarking, and SOC and System level implications. The candidate will work with ... SOC IPs Power requirements including power states, high level power tree & power sequence requirements. 3. Work...of low power design principles across RTL, design and system level . **Preferred Qualifications:** Preferred… more
- Vector Atomic (Pleasanton, CA)
- …team of physicists, electronics engineers, and optical designers to define requirements and select FPGA/ SoC parts + Assist in the design of custom PCBs based on ... modern FPGA/ SoC devices + Identify and address critical design issues to ensure robust board layouts + Create RTL, test benches, and EDA support files to meet… more
- NVIDIA (Santa Clara, CA)
- …of the Data-Center-on-a-Chip Architecture (DOCA). You will be among the very first to design systems for NVIDIA's next-generation SoC and take part in defining ... data science, and AI. What you'll be doing: + Architect, design , and develop innovative, scalable, performant hardware-accelerated software products to run… more
- Renesas (Milpitas, CA)
- …and ability to work in a technically challenging environment with other top performers to continue Intersil's development of industry leading power management IC's** ... This is an opportunity to contribute at a high level to the technical and commercial success of the...beyond traditional power management topics due to the embedded SOC nature of the products. Experience with firmware-enabled products… more
- Meta (Sunnyvale, CA)
- …8. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer,… more
- Vector Atomic (Pleasanton, CA)
- …quantum instruments. + Code and verify system controllers on ARM SoC . Develop user-space drivers, data acquisition pipelines, and robust control loops ... + Experience in Python, including common scientific libraries + Design and coding of control algorithms such as PID....etc. + Experience in C/C++ + Background working with SoC /FPGA devices. + Experience with Linux device drivers. +… more
- pony.ai (Fremont, CA)
- …functionality with EE engineers. + Develop driver and application software on MCU and SoC . + Analyze and triage low level system issues. Requirements + BS/MS ... Venture Partners inaugural "XB100" 2023 list of the world's top 100 private deep tech companies, ranking #12 globally....a network switch and router works + Strong software design and development skills including C, C++, Python, etc… more