- Expedite Technology Solutions, LLC (Santa Clara, CA)
- …* Architect and Create verification environments using System-Verilog and Universal verification methodology -UVM IPs and SoCs with embedded CPUs and analog ... knowledge in SV Assertions, UVM/OVM and functional code coverage. * SOC Verification experience using ARM Cortex Microcontroller is required. * Experience with… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, to firmware, and algorithms.We are seeking an SoC Modeling ASIC Engineer to support C++/Python modeling and software ... and mapping software pipelines to the dedicated hardware accelerators. **Required Skills:** SoC Modeling ASIC Engineer Responsibilities: 1. Analyze the software… more
- NVIDIA (Santa Clara, CA)
- We are looking for SOC Design Engineer ! The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a ... SOC ) group is looking for a top ASIC Engineer with a curiosity about SOC design...integration, chip build and assembly, and padring design and verification . You should have real passion for methodologies and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking to hire a senior verification architect to design verification methodology for our next generation SOCs with AI capabilities for ... and next generation SoCs. + Design and implement new verification methodology solutions, including TB architecture, test...engineer with a real passion for improving design verification efficiency and pushing barriers? If so, we want… more
- Amazon (Sunnyvale, CA)
- …STA) into SoC timing signoff flow. - Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners, Synthesis, Place & Route ... Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our...& Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA,… more
- Meta (Sunnyvale, CA)
- …in support of our industry leading virtual and augmented reality systems.As a Design Verification Engineer (DVEs), you will be a key contributor in planning, ... industry leading virtual and augmented reality systems. **Required Skills:** Design Verification Engineer Responsibilities: 1. Self sufficient and detail… more
- NVIDIA (Hillsboro, OR)
- We are now looking for a CPU Design Methodology Engineer ! The complexity of chip development has greatly increased over the years. We are now packing tens of ... NVIDIA CPU team is looking for a top ASIC Engineer with an interest in SOC design...and problem-solving skills + Experience in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design… more
- NVIDIA (Santa Clara, CA)
- …how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. The team develops and ... supports static RTL verification methodologies for RTL Lint and Logical Equivalence. As...limits of technology and performance for GPU, CPU and SoC markets. What you'll be doing: + Evaluate new… more
- Meta (Austin, TX)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Austin, TX)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification … more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Verification Engineer for our Tegra group! NVIDIA is seeking outstanding Senior Verification Engineers to verify the design ... writing UVM testbench from scratch and applying constraint random methodology in UVM test environment. + Highly proficient in...Stand Out From The Crowd: + UVM knowledge and SOC verification experience. + Ambitious and highly… more
- Meta (Austin, TX)
- …development cycles 12. 5. Verilog, SystemVerilog, C/C++ based verification and UVM methodology 13. 6. IP/sub-system or SoC level verification based on ... Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Develop functional... test plan. 2. Duties include: Define and implement IP/ SoC verification plans, build verification … more
- IBM (Research Triangle Park, NC)
- …to India for this opportunity. Relocation assistance will be provided. As a Functional verification engineer , you will be working on IBM server processors/ SOC ... like PCIE/CXL, DDR, Flash, Ethernet etc + AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric ...domain crossing verification + Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ + Knowledge… more
- Microsoft Corporation (Mountain View, CA)
- …servers, clients, and augmented reality. We are looking for a **Principal Design Verification Engineer ** to work on leading edge IP (intellectual property) ... and assertions to verify design correctness. + Develop Universal Verification Methodology (UVM) components to interface between...of experience in design verification with full verification cycle on complex System on Chip( SoC )… more
- Micron Technology, Inc. (Atlanta, GA)
- …are transforming how the world uses information to enrich life. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing ... best-known practices and communicate to all DRAM teams. + Performing verification processes with modeling and simulation using industry-standard simulators. Analyze… more
- Cisco (San Jose, CA)
- …You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification ... Who You Are * You are an ASIC Design Verification Engineer with 5+ years of related... verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development… more
- Siemens Digital Industries Software (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based on ... who like to interact with and influence others, possess strong design and/or verification background, requiring both in depth knowledge of HDL and HVL, as well… more
- Qualcomm (Austin, TX)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...plans based on the Architecture and Micro-architecture. + Develop Verification Methodology , ensuring scalability and portability across… more