- Power Integrations (San Jose, CA)
- Job Description: In this position, you will be responsible for supporting all IC design CAD tools, which include but not limited to Cadence schematic entry, ... license management, user support, and vendor interface. You will also work with IC layout designers in taping out physical layout design to mask shop. Education… more
- Power Integrations (San Jose, CA)
- In this position, you will be responsible for supporting all IC design CAD tools, which include but not limited to Cadence schematic entry, mixed mode circuit ... license management, user support, and vendor interface. You will also work with IC layout designers in taping out physical layout design to mask shop. Requirements:… more
- Broadcom (San Jose, CA)
- …and layout engineers to optimize layout for area and performance + Work with CAD , packaging and foundry teams in resolving layout and / or verification issues + ... required on technologies: 40nm, 16nm / 7nm FinFet -Knowledge of I/O, ESD, packaging, CAD setup, Cadence SKILL and Unix scripting is a plus -A team player,… more
- Capgemini (San Jose, CA)
- **Job Role: CAD Infrastructure Engineer for ASIC Design Engineer ** **Job Location: San Jose CA** **Job Summary:** We are seeking a skilled CAD ... The ideal candidate will be responsible for developing and maintaining the CAD infrastructure, ensuring efficient design workflows, and supporting the design and… more
- ManpowerGroup (San Jose, CA)
- Sr. Layout Engineer **SUMMARY:** A fast-growing Power Management division focusing on Power Loss Protection, PMICs, Motor Control, and Battery Management solutions ... and Industrial applications is seeking an experienced Principal Layout Engineer . **RESPONSIBILITIES:** + Layout of Power and Analog integrated...JI and SOI + Collaborate with Analog and Power IC design engineers in Asia and the US +… more
- Qualcomm (Santa Clara, CA)
- …and bump placement and optimize the package size. **Minimum Qualifications:** As the IC Package Design Engineer , you demonstrate fundamental knowledge or proven ... developers on feature development and bug resolution. + Explore, evaluate, and develop new CAD tools, design, and verification flow. + Partner with BU PD team to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for next generation ... Requirements: The student intern should have completed foundational coursework in Digital IC design, Computer Architecture and VLSI design. Exposure to VLSI design… more
- Celestica (San Jose, CA)
- …an unrelenting drive to find the way for our customers. **Let's engineer the future together** . Responsible for architecting, implementing, and supporting power ... work with SI engineers to define SI constraints, Guide CAD designers and bring-up and debug issues. + Set...create and maintain the preferred list + DC relevant IC selection, create and maintain the preferred list +… more