- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Improvement ... running chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... partitioning, timing budget generation, power planning, top-level PnR, CTS, block...from netlist to GDS + Understanding SI prevention, fixing methodology and implementation + Proficient in layout edit techniques… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for the ... blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. . Static and...Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and external teams… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of ... controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into the overall SOC design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- Amazon (Sunnyvale, CA)
- …and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of the… more
- Qualcomm (Santa Clara, CA)
- …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and power… more