- Cisco (San Jose, CA)
- …include: * Lead chip-level PNR activities, from floor planning , bump and rdl planning , power grid design to clock planning , routing, and timing ... join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the...chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results. * Work closely… more