- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Cisco (San Jose, CA)
- …noise, while managing ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA ... practices. * Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $100,100 to… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...practices. * Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Cisco (San Jose, CA)
- …as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 /hr. Location: ... Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all design phases of physical design… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer , you will contribute to all ... from RTL to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to… more
- Capgemini (Santa Clara, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, partitioning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Capgemini (Santa Clara, CA)
- **Location: San Clara, California.** **Job description:** The RTL Engineer performs detailed block design from system requirements and evolving specifications. ... checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA , PD and DFT teams to meet all functional requirements, performance, power,… more
- Google (Mountain View, CA)
- …ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon ... a must. The Role: We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have… more
- Broadcom (San Jose, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...power management. 4. Hands-on experience in physical design and STA 5. Well verse in EDA tools for physical… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... physical design, and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level...in PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
- Broadcom (San Jose, CA)
- …timing tool - Ability to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC networks and how they affect the ... Ability to understand and create timing diagrams Deep understanding of more advanced STA concepts - POCV/SOCV/LVF modeling of variation - MIS - multi input switching… more
- Google (Sunnyvale, CA)
- …cross-functional teams, including chip top design, physical design, Static Timing Analysis ( STA ), package, and system teams. + Experience with 2.5D/3D package design ... (eg, silicon interposer, silicon bridge, 3D die stacking, STA , Voltage budget). + Expertise in signal and power integrity for various high speed interconnects (eg,… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Qualcomm (Santa Clara, CA)
- …for the needs of the server product. As a CPU Floorplan and Integration Engineer , you will work with microarchitecture, RTL design and physical design teams to ... a team environment. + In-depth understanding of extraction, static timing analysis ( STA ), and electromigration and IR drop (EMIR) flows and methodologies. Preferred… more