- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep ... understanding of timing constraints, such as clock groups, various exceptions, clock... constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding ... Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing ...and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools… more
- Cisco (San Jose, CA)
- …or related experience * Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working ... from concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- Cisco (San Jose, CA)
- …development - Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation ... in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend...What You'll Do * Responsible for implementing the Hardware Design-for- Test (DFT) features that support ATE, in-system test… more
- Belcan (Palo Alto, CA)
- …expected operation sequences, and their corresponding results, including Register maps, Timing diagrams, Command sequences Develop test vectors based on ... Senior Hardware Engineer Job Number: 353813 Category: Electrical / Electronics...and invalid input scenarios, edge cases for register settings, timing and sequence requirements; enhance the test … more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- Control System Engineer Job ID 6186 Location SLAC - Menlo Park, CA Full-Time Regular **SLAC Job Postings** **Position overview:** Do you enjoy collaborating with a ... (LCLS) Directorate at SLAC is seeking a Control System Engineer to join the Engineering and Design controls team....of tools and applications for experiment laser control and timing control systems. LCLS is the world?s first hard… more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- Qualcomm (Santa Clara, CA)
- …positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools ... responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning,… more
- Meta (Sunnyvale, CA)
- …and verification. 3. Define timing constraints, run synthesis and static timing analysis. 4. Support the test program development, chip validation and ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...including UPF flow. 19. Experience with design synthesis and timing optimization. 20. Master's degree in Computer Science, Computer… more
- Broadcom (San Jose, CA)
- …with verification engineers and physical design teams to ensure functional correctness, timing closure, and overall design robustness, with a strong focus on ... specifications, focusing on efficient and robust design implementations. **Synthesis and Timing Closure:** + Perform synthesis and work with physical design teams… more
- Meta (Sunnyvale, CA)
- …Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop cutting-edge AMS ... augmented reality systems. **Required Skills:** Digital Mixed Signal Design Engineer Responsibilities: 1. Collaborate with AMS architects to define… more
- Broadcom (San Jose, CA)
- …DDR memory system development and debug is required. Expertise in HBM, DRAM manufacturing test and in-system DRAM test is also desirable. This position is ... DDR memory interfaces including the PHY, controller and embedded test capability. Direct experience with HBM memory is a...technology and ASIC design flow including Verilog simulation and timing analysis. Verilog experience is a plus. * Experience… more
- Qualcomm (Santa Clara, CA)
- …. Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and demodulators, transmit ... beamforming, timing and synchronization, RF impairment correction, adaptive filters ....with the verification engineers to develop unit-level and integrated-level test -benches . Debugging the designs in stand-alone and integrated… more
- Broadcom (San Jose, CA)
- …complex and cutting edge network switching ASIC DFx (Design for Test /debug & manufacturability) from DFT architecture, to implementation, verification, timing ... aggressively deliver low DPPM's, while optimizing the cost for test . Responsibilities + Drive the test quality...plus + Experience or familiarity in back-end chip design, Timing , CDC flows is a plus + Strong Pre/Post… more
- Amazon (Sunnyvale, CA)
- …around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of hard-working ... micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using innovative CAD tools and using the latest process… more
- TrustPoint (Mountain View, CA)
- …anti-jam capabilities. The improvements will support US Government position and timing service resiliency as well as enable next-generation commercial applications ... with our microsatellite based commercial infrastructure and innovative positioning and timing services. The Position With locations outside Washington DC and in… more
- Teledyne (Mountain View, CA)
- …Electronic Warfare (EW/ECM/CIED), Industrial, Missile/UAV, Radar, Satcom, Space, and Test and Measurement. Teledyne Microwave Solutions invests heavily in research ... and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design of integrated circuits… more
- Arrow Electronics (San Jose, CA)
- … Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/ Test ) handling, block and top level static timing analysis, ECO ... generation at top level, handshaking with blocks for timing /functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power… more