- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Design Verification Engineer (with modern Python programming)_… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level *Understanding constraints...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design … more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...hard IP identification, selection and integration 6. Collaboration with verification and emulation teams in test plan development and… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
- Meta (Menlo Park, CA)
- …applications. The role also involves partnering with Full Stack Software, Hardware, ASIC Design , Verification , Emulation, Pre/Post-Silicon Validation & ... build and scale silicon for data center applications.As an ASIC Engineer in the Silicon Lifecycle Engineering...to guide future improvements. 3. Work directly with the design & verification team to enable a… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...hard IP identification, selection and integration 5. Collaboration with verification and emulation teams in test plan development and… more
- Meta (Menlo Park, CA)
- …the architecture. 4. Work with a broad array of cross functional partners in ASIC design , verification , silicon bring-up, firmware and software development ... **Summary:** Meta Platforms Inc. is seeking an ASIC Engineer , Architecture to join our...in analyzing and driving power versus performance trade-offs in ASIC design . **Public Compensation:** $114,000/year to $166,000/year… more
- Google (Mountain View, CA)
- …SystemVerilog for ASIC designs. + Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments. Preferred ... qualifications: + Experience in creating detailed block-level design verification strategies and plans. + Experience creating or using verification … more
- US Tech Solutions (San Francisco, CA)
- …modeling preferred **Skills:** + UVM (Universal Verification Methodology) + FPGA tools + ASIC verification knowledge + Ethernet, PCIe + Python or C++ for UVM ... **Job Description:** + The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as… more
- Google (Mountain View, CA)
- …Knowledge of high performance and energy efficient design techniques. + Knowledge of ASIC Verification or DFT. Be part of a diverse team that pushes ... or Computer Science, with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks, reset checks and low… more
- Google (Mountain View, CA)
- … design tools. Minimum Qualifications: + At least 10 years experience in ASIC physical design flows and methodologies in advanced nodes. + Experience from ... can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development...+ Hands on experience and a solid understanding of ASIC physical design , physical design … more
- Google (Mountain View, CA)
- …such as speed, performance, power, area. + Good understanding of ASIC design flow including RTL design , verification , logic synthesis and timing ... can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development...micro-architecture definition. + 3+ years of experience in RTL design verification . + Experience with high performance… more
- Teledyne (Mountain View, CA)
- …for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design ... summarizing development and service issues + Advanced level experience with digital and ASIC design + Advanced level experience with RISC or ARM-based… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San… more
- Google (Mountain View, CA)
- …design concepts, and languages such as Verilog or SystemVerilog. + Experience with ASIC design methodologies for clock domain checks, reset checks and low ... field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or… more
- Meta (Menlo Park, CA)
- …cycle of multiple generations of products 13. 2+ years of experience with designing ASIC verification & bring up hardware. 14. 3+ years of expertise with ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our...suppliers, to define product roadmap and program. 2. Specify, design , and develop CPU/GPU/ ASIC based compute hardware… more
- Meta (Menlo Park, CA)
- …cycle of multiple generations of products 13. 2+ years of experience with designing ASIC verification & bring-up hardware. 14. 3+ years of experience with ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Network Hardware team. Our...suppliers, to define product roadmap and program. 2. Specify, design , and develop ASIC based network hardware… more
- Microsoft Corporation (Mountain View, CA)
- …validation and achieve its goals. + Work with Cross functional teams, Architecture, Design , Verification , Partner teams for project execution and also influence ... Artificial Intelligence Silicon Engineering team is seeking a **Senior Validation Engineer ** to deliver premium-quality designs once considered impossible. We are… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. . Minimum of 5 years in Sales Pursuit Management. ... foundries, EDA companies, and IP providers. . Background in ASIC Design or Semiconductor Technology R&D is...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more