- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design ...**Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Design Verification Engineer (with modern Python programming)_ **Location:**… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... techniques to improve RTL code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and ASIC … more
- Meta (Menlo Park, CA)
- …Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors 6. ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Mechanical/Thermal modeling focus...ASIC R&D and manufacturing to drive the mechanical/thermal design using advanced FEA of new ASICs, and make… more
- Meta (Menlo Park, CA)
- …entire Silicon Lifecycle to build and scale silicon for data center applications.As an ASIC Engineer in the Silicon Lifecycle Engineering team, you will be part ... The role also involves partnering with Full Stack Software, Hardware, ASIC Design , Verification, Emulation, Pre/Post-Silicon Validation & Systems teams… more
- Meta (Menlo Park, CA)
- **Summary:** Meta Platforms Inc. is seeking an ASIC Engineer , Architecture to join our Infrastructure organization. This organization is responsible for building ... expert engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Machine Learning Architecture (PhD) Responsibilities: 1.… more
- GE HealthCare (Palo Alto, CA)
- …(MR) systems? Join our innovative MR Hardware Team as a Lead Electrical Engineer - Wireless and be at the forefront of developing state-of-the-art wireless modules ... and interfaces! About the Role: As a Lead Electrical Engineer - Wireless, you will play a pivotal role in the development of wireless solutions within MR systems.… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking a versatile Hardware Engineer to join our Accelerator Design team. Our mission is backed by a massive hardware infrastructure. Our ... our cutting-edge data centers, affecting billions of users. **Required Skills:** Hardware Engineer (Accelerator Design ) Responsibilities: 1. Specify, design ,… more
- Google (Mountain View, CA)
- …or Computer Science, with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks, reset checks and low ... power design . + Experience in ASIC design flows and methodologies. + Domain knowledge in one of these areas: Processor Cores, Buses/Fabric/NoC, Debug/Trace,… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced Silicon Packaging design Engineer for its Ecosystem and Technical Operation team to support the development of ... create as part of a world-class engineering team. **Required Skills:** Silicon Packaging Design Engineer Responsibilities: 1. Perform package design for… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San… more
- Teledyne (Mountain View, CA)
- …for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design ... development and service issues + Advanced level experience with digital and ASIC design + Advanced level experience with RISC or ARM-based microcontrollers +… more
- Google (Mountain View, CA)
- …design concepts, and languages such as Verilog or SystemVerilog. + Experience with ASIC design methodologies for clock domain checks, reset checks and low ... practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. + 5… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design ... MS or Ph.D. in Electrical Engineering with a minimum of eight years of CPU/GPU/ ASIC implementation + Proficiency in TCL scripting + Proficiency in chip front-end and… more
- US Tech Solutions (San Francisco, CA)
- **Job Description:** + The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, ... functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the...+ UVM (Universal Verification Methodology) + FPGA tools + ASIC verification knowledge + Ethernet, PCIe + Python or… more
- Meta (Menlo Park, CA)
- …and remote teams and suppliers, to define product roadmap and program. 2. Specify, design , and develop CPU/GPU/ ASIC based compute hardware solutions, and ASIC ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our...Support hyper-scale deployment and obtain learning for next generation design . 5. Collaborate with open source hardware community to… more